verilog, verilogger, file with 'v' extension

[PG1995]

Thanks a lot.

It is better to use the explicit connections like .Y(Y1) because late when you change something in your code and mess up the order it will keep working and not break up, just because the order of the parameters changed.

I understand your point but for the time being I will stick to the way I have already written it assuming it's doesn't cause any compilation error.

Yes, you are right. I also think that using include directive isn't necessary as long as the other file is included in the project.

I'm getting the following errors for the code at the bottom. Please help me with it.

two_to_1_mux mux1(Y1,A,B,Sel0,En);

two_to_1_mux mux2(Y2,C,D,Sel0,En);

two_to_1_mux mux3(Y3,Y1,Y2,Sel1,En);

By the way, the file "two_to_1_mux" contains the code shown in post #13 above but I have omitted the "stimulus" part of code which is used for simulation. Thank you.

 

[kubeek]

You need to post the whole code, otherwise error on line 3 makes no sense.

 

[PG1995]

My apologies for the confusion. Please ignore my previous post.

I'm getting no error for the code below. Do you think it's logically correct? Now I'm going to write stimulus for it.

//4 to 1 mux using 2 to 1 muxs

module four_to_one(Y3,A,B,C,D,Sel,En);

input [3:0]A;
input [3:0]B;
input [3:0]C;
input [3:0]D;

input [1:0]Sel;

input En;

output [3:0]Y3;
reg [3:0]Y;

two_to_1_mux mux1(Y1,A,B,Sel[0],En);

two_to_1_mux mux2(Y2,C,D,Sel[0],En);

two_to_1_mux mux3(Y3,Y1,Y2,Sel[1],En);

endmodule

By the way, the file "two_to_1_mux" contains the code shown in post #13 above but I have omitted the "stimulus" part of code which was used for simulation. Thank you.

 

[kubeek]

reg [3:0]Y; seems superfluous, otherwise it looks ok.

 

[PG1995]

Thanks.

I'm getting the following errors for the code shown below. Please help me with it.

//4 to 1 mux using 2 to 1 muxs

module four_to_one(Y3,A,B,C,D,Sel,En);

input [3:0]A;
input [3:0]B;
input [3:0]C;
input [3:0]D;

input [1:0]Sel;

input En;

output [3:0]Y3;
reg [3:0]Y3;

Sel0 = Sel[0];                                               //  line #17
Sel1 = Sel[1];                                              // line #18

two_to_1_mux mux1(Y1,A,B,Sel0,En);

two_to_1_mux mux2(Y2,C,D,Sel0,En);

two_to_1_mux mux3(Y3,Y1,Y2,Sel1,En);

endmodule


//stimulus

module testbench;

  reg [3:0]A;
  reg [3:0]B;
  reg [3:0]C;
  reg [3:0]D;
  reg [1:0]Sel;
  reg En;
  wire [3:0]Y3;


  four_to_one fourMux(Y3,A,B,C,D,Sel,En);
  initial
  begin
  A<=4'b1111;
  B<=4'b1010;
  C<=4'b1100;
  D<=4'b0011;
  En<=1;

  Sel=00;
  #20 Sel=01;
  #20 Sel=10;
  #20 Sel=11;
  #20 $finish;
  end

endmodule

 

[kubeek]

first of all I don't see sel0 and sel1 defined anywhere. Second thing is that those two lines would either have to be inside an always block, or they would have to be assign Sel0 = Sel[0]; // line #17
I'm not too sure on this one, I can't say I am a seasoned verilog programmer, usually I try over and over until it compiles and works the way I want.
Here is some code I made over the last three or four months, it has a lot of modules like timers and other stuff, also a bi-directional i/o port. You can find there a testbench that reads bytes from a file. It is made for xilinx coolrunner II CPLD.
I am planning to use it as a front end for communication with RFID card reader (pretending to be a card), but I doubt that it would be useful to anyone at this stage.

 

[PG1995]

Thanks a lot.

You might not be a seasoned verilog programmer but still you know enough to help me and that's what matters to me!

I have xilinx installed on my other computer but I don't use it. It must have taken you a lot of time to write all those codes. Good luck with your plan!

I'm getting only one error now. Please help me with it.

//4 to 1 mux using 2 to 1 muxs

module four_to_one(Y3,A,B,C,D,Sel,En);

input [3:0]A;
input [3:0]B;
input [3:0]C;
input [3:0]D;

input [1:0]Sel;

input En;

output [3:0]Y3;
reg [3:0]Y3;

two_to_1_mux mux1(Y1,A,B,Sel[0],En);

two_to_1_mux mux2(Y2,C,D,Sel[0],En);

two_to_1_mux mux3(Y3,Y1,Y2,Sel[1],En);                                         // line #21

endmodule

//stimulus

module testbench;

  reg [3:0]A;
  reg [3:0]B;
  reg [3:0]C;
  reg [3:0]D;
  reg [1:0]Sel;
  reg En;
  wire [3:0]Y3;

  four_to_one fourMux(Y3,A,B,C,D,Sel,En);
  initial
  begin
  A<=4'b1111;
  B<=4'b1010;
  C<=4'b1100;
  D<=4'b0011;
  En<=1;

  Sel=00;
  #20 Sel=01;
  #20 Sel=10;
  #20 Sel=11;
  #20 $finish;
  end

endmodule

 

[kubeek]

delete that reg [3:0]Y3; line
Y3 in this module is just a wire, so it cannot be a reg at the same time.

 

[PG1995]

Okay. The error is gone once I deleted that line but I don't get it. If you look at the code shown in post #13, you will see that there I declared Y as a wire and also a register and it didn't result in any error. So, why do I get error in this case? Perhaps, the reason being that in the original module source file, Y is already a register so the register declaration isn't really required in sub-modules. Thanks.

Regards
PG

 

[kubeek]

The difference is that you have two different modules, even though within a single file, so both Y are separate things. In module two_to_1_mux Y needs to be reg, because you are writing a value to it.
In testbench it needs to be just a wire, because it only connects output of mux to (nothing) but it would be used to connect it to the output of testbench if it had one (or input of some other instance).

 

[PG1995]

Thanks a lot for the help, kubeek,

It was fun doing verilog today. I also need to do ripple carry adder but I think I better do it some other time.

Best wishes
PG

 

[PG1995]

Hi kubeek

Q1:
I have found a big error with the code of 4-bit four-to-one mux you helped me with. I have checked the code of 4-bit two-to-one mux separately and it works okay. It means that the error lies somewhere in the code for four-to-mux. You can see here that output Y3 is "1" when it should be "F", and it's "0" when it should be "A" and so on. Please help me with it. Thanks.

//4-bit 2x1 Mux

module two_to_1_mux(Y,A,B,Sel,En);

input [3:0]A;
input [3:0]B;
input Sel,En;
output [3:0]Y;
reg [3:0]Y;

always @(En or Sel or A or B)
  if(En==1)begin
  if (Sel==0)
  Y <= A;
  else
  Y <= B;
  end
endmodule

//4-bit 4 to 1 mux using 2 to 1 muxs
//we will use the code for 2-to-1 mux given above

module four_to_one(Y3,A,B,C,D,Sel,En);

input [3:0]A;
input [3:0]B;
input [3:0]C;
input [3:0]D;

input [1:0]Sel;

input En;

output [3:0]Y3;

two_to_1_mux mux1(Y1,A,B,Sel[0],En);

two_to_1_mux mux2(Y2,C,D,Sel[0],En);

two_to_1_mux mux3(Y3,Y1,Y2,Sel[1],En);

endmodule


//stimulus

module testbench;

  reg [3:0]A;
  reg [3:0]B;
  reg [3:0]C;
  reg [3:0]D;
  reg [1:0]Sel;
  reg En;
  wire [3:0]Y3;


  four_to_one fourMux(Y3,A,B,C,D,Sel,En);
  initial
  begin
  A<=4'b1111;
  B<=4'b1010;
  C<=4'b1100;
  D<=4'b0011;
  En<=1;

  Sel=00;
  #20 Sel=01;
  #20 Sel=10;
  #20 Sel=11;
  #20 $finish;
  end

endmodule

Q2:
I have written the following code for a full adder but it's full of errors. Could you please help me with it? I see that some of the error lines point out that "...has already been declared". In the past, I used to use the same identifiers or names for inputs and outputs both in the main code and the stimulus.

//full adder

module full_adder(S,C_out,A,B,C_in);

  input A, B, C_in;
  output S, C_out;
  reg S, C_out;

  wire w1;

  always @(A or B or C_in)
  begin
  assign w1 = A^B;
  assign S = w1^C_in;
  assign C_out = (w1 & C_in) | (A & B);
  end

endmodule


//stimulus

module testbench;

  full_adder FullAdder(S,C_out,A,B,C_in);

  reg A, B, C_in;
  output S, C_out;

  initial
  begin
  A=0; B=0; C_in=0;
  #20 A=0; B=0; C_in=1;
  #20 A=0; B=1; C_in=0;
  #20 A=0; B=1; C_in=1;
  #20 A=1; B=0; C_in=0;
  #20 A=1; B=0; C_in=1;
  #20 A=1; B=1; C_in=0;
  #20 A=1; B=1; C_in=1;
  #20 $finish;

endmodule

Errors:

 

[PG1995]

UPDATE:
Q1 has been resolved. Thanks.

 

[kubeek]

Ok, so some things about Q2.
in full adder either use those assign statements outside the always block and remove reg from S and c_out, or make w1 a reg. You cannot assign to a wire inside a procedural block (always block)

In testbnch - You need to define wires and regs first then instantiate components, not the other way or even mixed. Also you´re missing end before endmodule.

 

[PG1995]

Thank you, kubeek. The code for a full adder works now and output waveform is good.

Now I have tried to code a ripple carry adder. You can see here that the displayed values of "A" and "B" are incorrect; A should been 1111b=F and B should have been 1010b=A. Besides this, there are some other logical errors. Please help me. Thanks.

//full adder

module full_adder(S,C_out,A,B,C_in);

  input A, B, C_in;
  output S, C_out;
  reg S, C_out;

  reg w1;

  always @(A or B or C_in)
  begin
  assign w1 = A^B;
  assign S = w1^C_in;
  assign C_out = (w1 & C_in) | (A & B);
  end

endmodul

//4-bit ripple carry adder
//we will use full adder code given above for instantiation

module four_bit_ripple_adder(S,C_out,A,B,C_in);

  input [3:0]A;
  input [3:0]B;
  input C_in;
  output C_out;
  output [3:0]S;

  full_adder adder1(S[0],C_out0,A[0],B[0],C_in<=0);

  full_adder adder2(S[1],C_out1,A[1],B[1],C_out0);

  full_adder adder3(S[2],C_out2,A[2],B[2],C_out1);

  full_adder adder4(S[3],C_out3,A[3],B[3],C_out2);

endmodule


//stimulus

module testbench;

  reg [3:0]A;
  reg [3:0]B;
  wire [3:0]S;

  four_bit_ripple_adder fourBit(S,C_out,A,B,C_in);

  initial
  begin
  A=1111;
  B=1010;
  #20 $finish;
  end

endmodule

 

[kubeek]

I think it is time for you to learn how to troubleshoot your designs. Does your software alloow you to see what is going on inside the fourBit component and underlying adders? Can you check that C_in actually has the value you think it has? If not, then I suggest you try using for example the xilinx tools, their simulator is pretty nice to use.

Also, shouldn´t you be setting the C_in in the testbench, and not in the adder? An adder needs to have that bit accesible so that you can use carry and do subtraction as well.

 

[PG1995]

Hi kubeek

The following is making Verilogger program to crash every time I try to compile it. Could you please help me with it? I believe there is some serious error in the stimulus code because otherwise the code compiles fine. Thank you.

// gated d-latch
//also check image file

  module D_Latch(Q_out,D_data,En);

  input D_data, En;
  output Q_out;

  reg Q_out;

  always @(En or D_data)  begin
  if (En == 1)  begin
  if (D_data == 0)
  Q_out <= 0;
  else
  Q_out <= 1;  end
  else  
  Q_out <= Q_out;
  end

  endmodule

//Stimulus

  module testbench;

  reg D_data; reg En;
  wire Q_out;

  D_latch d_latch1(Q_out,D_data,En);

  initial
  begin
  En <= 1;
  D_data <= 0;
  #20
  D_data <= 1;
  #20
  En <= 0;
  #20 $finish;
  end

  endmodule

 

[kubeek]

I don't see anything wrong with that code. You might want to try making a new project and compile it again, or use some other software like xilinx ISE or Modelsim.
edit: ok I found the problem, you are instantiating a wrong name, you have lower cas L there. Still i would rather use software that tells me where the problem is instead of just crashing.

 

[PG1995]

Thank. It works now.

I was trying to write another code for a clock module which gives 40 units delay. But I don't know why it gives me errors. Could you please help me? Thanks.

module clock_40();

  int clk;  //line #6

  always @(1) begin
  #40  clk = 0;  //line #9
  #40  clk = 1;  //line #10
  end

  endmodule

 

[kubeek]

I would start with the error on line 6, then recompile and sort the next one.
always @(1) is nonsense, this is not a while loop in C. use simply always begin ... end
Also i am not sure if int is a reserved word, use integer instead which will definitely work.