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.But we do not know what circuits you are testing.
Maybe you also do not know what circuits you are testing
The circuit have Flip Flops, That I have to Reset and Enable , because If I don't Reset and Enable them they will STORE the wrong Logic State even If I did change the INPUT from the Receptacle connector
Are you fixing ANYTHING?True, I don't know what the expected INPUT and OUTPUT's are suppose to be, Plus I have no idea what the inputs and outputs are expected to be since i don't have a KGB Known good board.
They get troubleshot by looking at the logic levels and when an event happens seeing if they change states
Are you fixing ANYTHING?
Why are you and your manager causing more damage by randomly forcing logic signals when you do not know what you are doing?
If inputs A & B are logic High what will Vout be? What will happen if I try to force Vout to its alternate state? Make R2 1K Ohm. If you would like I'll string a few together but the end result will be the same.
For some applications the S&R (Set and Reset are tied high or low, some use a momentary button and some may be set or reset by another chip.
Again, you can't just apply high and low to see what may or may not happen unless you understand the circuit.
So with Q3 turned On it is at Ground for Vout or really close anyway. If I place a High (5 Volts) at Vout I will toast Q3 and that is the end of the gate.
SET and RESET are inputs, not outputs. Inputs are expected to be driven high or low.Can I damage a Flip flop by FORCING a High or LOW? will this damage the Set or Reset ( transistors inside )?
1) The NPN output transistor is turned on. The collector resistor is connected to +5V then the collector is forced to +5V. Then how much current is there in the collector resistor? Why did Billy even talk about the collector resistor?
2) Why does Billy say there is a short parallel to the output transistor when the output transistor and the forcing are in series?
3) Why does Billy say that the output transistor is sinking current when its collector is forced to +5V in either logic state LOW or HIGH when the output transistor is not even turned on when the inputs turn it off?
One end of the collector resistor is connected to +5V and you are forcing the collector end of the resistor to +5V.I was talking about the voltage drop ACROSS the collector resistor , not the voltage drop referenced to ground
Again you are COMPLETELY WRONG!How can the forcing be in series? it's a parallel path when your force it to VCC or force it to ground , it's not a series path
Again, you are COMPLETELY WRONG!When both inputs are HIGH, the output transistor is turned OFF , when both inputs are LOW , the output transistor is Turned ON
Again, you are WRONG!When the output transistor is OFF = a LOW logic level
One end of the collector resistor is connected to +5V and you are forcing the collector end of the resistor to +5V.
Then how much voltage is dropped ACROSS it?
The NPN output transistor is turned on so it is trying to make its collector voltage as low as it can. Then you are forcing its collector to +5V in series.
Again, you are WRONG!When both inputs are HIGH, the output transistor is turned OFF , when both inputs are LOW , the output transistor is Turned ONAgain, you are COMPLETELY WRONG!
Look at how its transistors work, lookup post #108 and lookup the logic of a NAND gate.
When the output transistor is OFF = a LOW logic level
1. Short the point to ground, and take a chance on doing damage or otherwise invalidating the test.
2. Cut traces to isolate the point from any outputs and then short it to ground.
3. Lift a pin from a chip, similar to cutting a trace.
When you force the voltage at one end of a resistor to be the same voltage that is at its other end then it does not matter if the transistor is on or off.ZERO , are u talking about when the transistor is ON or OFF?
No, because when you force the voltage at one end of a resistor to be the same voltage that is at its other end then you are simply shorting the resistor.So the Collector resistor tied to +5 is not a path or branch?
But you described the logic of an AND gate, not a NOR gate.Sorry I thought we were talking about a NOR GATE
No, because you said, "When both inputs are HIGH, the output transistor is turned OFF."But if you look at my answers using a NOR gates truth table i should be right about how the output transistor works
When you force the voltage at one end of a resistor to be the same voltage that is at its other end then it does not matter if the transistor is on or off.
No, because when you force the voltage at one end of a resistor to be the same voltage that is at its other end then you are simply shorting the resistor.
The current path is from the forcing voltage in series through the turned on transistor to ground. The collector resistor has nothing to do with it.