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Current Circuits, DVM meter will short out when measuring on current circuits

Discussion in 'General Electronics Chat' started by Billy Mayo, Dec 17, 2013.

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  1. audioguru

    audioguru Well-Known Member Most Helpful Member

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    But we do not know what circuits you are testing.
    Maybe you also do not know what circuits you are testing.
     
  2. Billy Mayo

    Billy Mayo Member

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    .

    True , I don't know what the expected INPUT and OUTPUT's are suppose to be from the Connector Receptacle has 40 pins that I connect a PCB board to. There is not way I can Disconnect the inputs from the Receptacle connector , Plus I have no idea what the inputs and outputs are expected to be since i don't have a KGB Known good board.

    The circuit have Flip Flops, That I have to Reset and Enable , because If I don't Reset and Enable them they will STORE the wrong Logic State even If I did change the INPUT from the Receptacle connector

    How would u approach This? the Logic IC input pins have traces that go directly to the Receptacle connector without having any resistors in series , so there is no way I can disconnect the inputs unless i cut traces or Lift Pins from a dual inline package which is hard to lift pins up from right?
     
  3. Reloadron

    Reloadron Well-Known Member Most Helpful Member

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    Billy, below is a typical NAND circuit.

    TTL NAND Ckt.png

    If inputs A & B are logic High what will Vout be? What will happen if I try to force Vout to its alternate state? Make R2 1K Ohm. If you would like I'll string a few together but the end result will be the same.

    Yeah, I have designed several circuits like that. You can for example push a button and reset them and they wait for an event pulse to toggle. Then they need reset again. They get troubleshot by looking at the logic levels and when an event happens seeing if they change states. You know what the circuit is and what it does so it is just a matter of seeing if the logic behaves as expected.

    Ron
     
  4. dave

    Dave New Member

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  5. audioguru

    audioguru Well-Known Member Most Helpful Member

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    Are you fixing ANYTHING?
    Why are you and your manager causing more damage by randomly forcing logic signals when you do not know what you are doing?
     
  6. Billy Mayo

    Billy Mayo Member

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    I don't have a push button or a switch to change the RESET button for the flip flops or the Enable Pin

    Is it safe to FORCE a voltage or ground the RESET pin on a flip flop , counter, etc. ?

    Yes I am, All kinds of circuits that don't have KGB known good boards , so I don't know what the EXPECTED inputs or outputs of the circuit is suppose to be from start inputs to the end outputs

    Cause he tells me what to do, My Manager is INEPT , not saying that i'm not , but he has worked there for 10yrs and he shouldn't be INEPT

    My Last manager tested logic circuits just like this too, we have went over this FORCING logic levels before , they pick up bad troubleshooting habits and that's why i present them to forums to see what educated techs do
     
  7. Billy Mayo

    Billy Mayo Member

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    a logic probe has a pulse stretcher circuit, what does this do? An oscilloscope doesn't have a "pulse stretcher circuit" so what is it missing when measuring logic levels?
     
  8. Billy Mayo

    Billy Mayo Member

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    Ok there is more of a voltage drop across Q3 ( output transistor ) when you force V out to an alternate state , because the Transistors collector will have close to 5 volts , 5 volts divided by collectors resistor.

    What will have is a VCC to ground short in parallel will Q3 ( output transistor )

    The Current is SINKING into Q3 ( output transistor ) in either logic state LOW or HIGH, VCC +5 volts is SINKING into Q3

    LOW logic state = +5 VCC sinking into the output transistor Q3
    HIGH logic state= + 5 VCC sinking into the output transistor Q3
     
  9. Reloadron

    Reloadron Well-Known Member Most Helpful Member

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    Hi Billy, if A and B are high then Vout will be a logic Low. Truth table for a NAND gate. So with Q3 turned On it is at Ground for Vout or really close anyway. If I place a High (5 Volts) at Vout I will toast Q3 and that is the end of the gate. That is it and that is why you can't play this game of forcing logic levels. Now in that instance if the Vout was high then yes, I could force it low. The trick is knowing what you have. You can't just run through a circuit arbitrarily forcing highs and lows.

    Flip Flops are another animal. They all depend on how thay are used in a circuit. For some applications the S&R (Set and Reset are tied high or low, some use a momentary button and some may be set or reset by another chip. Again, you can't just apply high and low to see what may or may not happen unless you understand the circuit.

    Ron
     
  10. Billy Mayo

    Billy Mayo Member

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    Can I damage a Flip flop by FORCING a High or LOW? will this damage the Set or Reset ( transistors inside )?

    True, I don't have a senior tech next to me to walk me through and understand the circuit or know how the circuit works

    That's why my manager wants me to arbitrarily forcing highs and lows , on the inputs to see what the outputs do and to force highs or lows on the set and reset pins on flip flops and see what the outputs do

    We don't have a KGB known good board to compare it to
     
  11. Billy Mayo

    Billy Mayo Member

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    Ok , but that goes back to my question as to why a logic pulsar will work when FORCING a HIGH logic level on a Vout that is Low , why doesn't it Toast Q3 output transistor ?
     
  12. audioguru

    audioguru Well-Known Member Most Helpful Member

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    I wish Ron didn't delete his post showing an open-collector NAND gate circuit because Billy's answer in post #107 shows that Billy knows NOTHING about electronics:

    1) The NPN output transistor is turned on. The collector resistor is connected to +5V then the collector is forced to +5V. Then how much current is there in the collector resistor? Why did Billy even talk about the collector resistor?

    2) Why does Billy say there is a short parallel to the output transistor when the output transistor and the forcing are in series?

    3) Why does Billy say that the output transistor is sinking current when its collector is forced to +5V in either logic state LOW or HIGH when the output transistor is not even turned on when the inputs turn it off?
     
  13. audioguru

    audioguru Well-Known Member Most Helpful Member

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    SET and RESET are inputs, not outputs. Inputs are expected to be driven high or low.
    But if you force a high or low then you will probably damage the output of the logic IC that drives them.
     
  14. Billy Mayo

    Billy Mayo Member

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    I was talking about the voltage drop ACROSS the collector resistor , not the voltage drop referenced to ground

    How can the forcing be in series? it's a parallel path when your force it to VCC or force it to ground , it's not a series path

    When both inputs are HIGH, the output transistors is turned OFF , when both inputs are LOW , the output transistor is Turned ON

    When the output transistor is OFF = a LOW logic level
    When you FORCE a low to a HIGH = the transistors collector is at +5 volts? the transistor is turned OFF it's close to zero, there is no current path because the transistor is off which breaks the path from Vcc to ground

    When the output transistor is ON = a HIGH logic level
    When you FORCE a High to a low = the transistors collector is at +5 volts and when your jumper a ground to force a low this is a parallel path not a series path
     
  15. audioguru

    audioguru Well-Known Member Most Helpful Member

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    One end of the collector resistor is connected to +5V and you are forcing the collector end of the resistor to +5V.
    Then how much voltage is dropped ACROSS it?

    Again you are COMPLETELY WRONG!
    The NPN output transistor is turned on so it is trying to make its collector voltage as low as it can. Then you are forcing its collector to +5V in series.

    Again, you are COMPLETELY WRONG!
    Look at how its transistors work, lookup post #108 and lookup the logic of a NAND gate.

    Again, you are WRONG!
    You do not understand how a simple common-emitter transistor works.
     
  16. Billy Mayo

    Billy Mayo Member

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    ZERO , are u talking about when the transistor is ON or OFF?

    So the Collector resistor tied to +5 is not a path or branch?



    Again, you are WRONG!
    You do not understand how a simple common-emitter transistor works.

    Sorry I thought we were talking about a NOR GATE

    But if you look at my answers using a NOR gates truth table i should be right about how the output transistor works
     
  17. Billy Mayo

    Billy Mayo Member

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    Is there any other ways?

    1.) Can I turn the POWER OFF on the circuit
    2.) Inject an external power supply#1 on the VCC to ground rails, of the same supply voltage as when the circuit is ON
    3.) Then I can use another external power supply#2 to inject logic High levels on the inputs, so I can test if the logic IC chip is working or not

    I do need to verify if the Flip flops are working too, which I need to Inject a voltage level to the SET and RESET pins so I can make sure they are storing the logic levels and outputting them compared with their truth table

    Bottom line I'm trying to Verify each Logic IC chip one by one with the power off but trying to Inject it with two different power supplies

    Don't you think this approach will work?
     
  18. audioguru

    audioguru Well-Known Member Most Helpful Member

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    When you force the voltage at one end of a resistor to be the same voltage that is at its other end then it does not matter if the transistor is on or off.

    No, because when you force the voltage at one end of a resistor to be the same voltage that is at its other end then you are simply shorting the resistor.
    The current path is from the forcing voltage in series through the turned on transistor to ground. The collector resistor has nothing to do with it.

    But you described the logic of an AND gate, not a NOR gate.

    No, because you said, "When both inputs are HIGH, the output transistor is turned OFF."
    When the output transistor is turned off then the collector resistor pulls up its output to be high. But the output of an AND gate is high when both inputs are high.
    Anyway you are also wrong about the transistor because when both inputs are high then the output transistor IS TURNED ON.
     
  19. Billy Mayo

    Billy Mayo Member

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    This is for all gates positive logic and negative logic
    output Transistor ON = LOW logic level
    output transistor OFF= HIGH logic level

    Some gates ADD the inputs and other Gates Multiple the inputs

    What determines the adding or Multiplying inside the GATE?

    Because inside the gates the transistor or mosfet just turns ON or OFF , but what ADDs them or Multiplys the two inputs together to get an output?
     
  20. Billy Mayo

    Billy Mayo Member

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    ya but you said the transistor is working really hard when it's off or on , you're overloading the output transistor when its on or off and the transistor is sinking or supplying the current when it's on or off

    True

    A short that is a series short is called a shunt
     
  21. ChrisP58

    ChrisP58 Well-Known Member

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    Logic outputs, either TTL or CMOS, are typically of two types. Either totem pole or open collector (open drain for cmos).

    Totem pole output have two transistors. An upper transistor from Vcc to the output, and a lower transistor from the output to ground. The upper transistor is ON when the output is HIGH. The lower transistor is ON when the output is LOW. In both cases the opposite transistor is OFF. More than one totem pole outputs should not be paralleled since, if the two outputs were different states, would put an ON upper transistor in series with an ON lower transistor which would cause a short from Vcc to gnd.

    Open collector (drain) outputs have only the lower transistor. When the output is LOW the transistor is ON. When the transistor is OFF, the output is open. You need to use a pullup resistor to make the output actually be HIGH. Open collector outputs may be paralleled since there is no conflict with one out being LOW and other outputs being HIGH. The net is lLOW if any of the outputs is LOW, and high only if ALL of the outputs are in the open state, when the pullup resistor makes the net HIGH.

    A logic pulser actually does force a net with a LOW output HIGH, and a HIGH output LOW, but does so with a very short pulse (typically a few microseconds) so that the output that it is working against is not damaged.

    A logic probe does have a pulse stretcher. This is needed to make a pulse that would be far to short for a human to see long enough to do so. An o'scope doesn't have anything called a pulse stretcher, but can accomplish the same thing by storing a pulse, as well as letting you see the pulse timing and shape.
     
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