Billy Mayo
Member
true, but isn't a pull up or pull down resistor forcing the logic state to go high or low?
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No.true, but isn't a pull up or pull down resistor forcing the logic state to go high or low?
A circuit that needs an output pullup resistor is missing the transistor that other circuits have in their output to make it high, so a resistor is added from the output to the supply voltage to make it high when the transistor that pulls down the output is turned off.
I have never seen a circuit that needs a pull-down resistor but it would also be missing an output transistor.
I thought a Logic Pulsar can Force a Logic HIGH either TTL or CMOS to a pulsing signal right?
This may sound unusual but it is an unfortunate fact for digital circuits. If you take the simple case of a chip being clocked by the output of another, the clock line is being taken HIGH and then LOW during the operation of the circuit.
If you halt the circuit when the output is LOW, it will be very difficult to pull the line HIGH because it is being kept LOW by the output transistors of the driving chip.
These transistors have a certain amount of ability to keep the line LOW and this is called SINKING ABILITY. For TTL this can be as much as 45mA and for CMOS it will be up to about 25mA.
This means we would have to put a signal on the line and deliver more than 25 mA or 45mA to pull it HIGH.
The output transistors would not like this and having a capability of delivering 45mA to a circuit could prove to be damaging to lots of other parts of the circuit.
The LOGIC PULSER is built around a CD 4060, 14-stage divider chip which has an inbuilt oscillator. With the addition of 3 components, the oscillator drives a string of 14 flip flops. The first output pin comes from the output of the 4th flip flop and this means the clock frequency is divided by 8.
From there it is divided further and an output is available from flips flops 5 to 14 (except 12).
We have used Q4, Q5, Q6, Q8, Q10, Q12, and Q14 in our project and have found these to be the most suitable for producing pulse trains.
Each output of the chip is taken to a switch on the 8-way DIP switch package and then diode gated together to form an OR gate.
A transistor buffer passes the signal to the probe tip where a 1k resistor is present to prevent damage to the probe if probing a power rail etc.
By turning ON various combinations of switches, you can produce a wide range of tones from a whistle to a 1Hz pulse.
You can modulate the tone by tuning on additional switches to produce 'chirping' or 'phone-ringing' tones. This has the effect of delivering a HIGH pulse modulated by LOW pulses, at the same time.
I troubleshooted (troubleshot?) logic by knowing what the output of a logic device should do and seeing it do it, then seeing if the logic IC it feeds does what it is supposed to do.
Thats a nice circuit Ron, I have a logic probe, its handy for when i just want a quick yes no type answer. For most other thing's i use a scope, mainly because i like to see what is going on. I might have a go at building that circuit, could be handy now and then.
thanks
You should never force an output to the other state on any chip you can blow the output and the chip will no longer work.Then its safe and ok to FORCE logic HIGHS to logic low for this types of logic gates right?
This thread is getting silly because Billy confuses a TTL gate with a COMPLETELY DIFFERENT Cmos gate.Ok I get it, so when you force a logic HIGH to a logic low it increase the current very high which causes heat , so it damages the output transistor or mosfet
We simply learned the truth table of an OR gate and the different truth table for a NOR gate. The same for AND and NAND. why can't you learn this simple stuff?truth tables that are Positive logic and others that are Negative Logic.
It gets really confusing for me.
You got to remember you guys have got this second hand and it doesn't come easy to others
So a logic pulser really doesn't "force" anything.
You should never force an output to the other state on any chip you can blow the output and the chip will no longer work.
What you need to do is change the inputs to get the output to change and work your way down the series of chips.
Normal troubleshooting of logic gates starts at the inputs and works its way to the outputs until a fault is found.
You should never need to force an output if you use proper troubleshooting techniques.
Then you can destroy a TTL output if you force it high OR if you force it low.
Its available output current is high at high supply voltages which can destroy it if you force an output high OR force it low.
Sometimes an ordinary TTL logic gate that has an active high and active low output uses a pullup resistor to pull its output voltage higher than its normal 2.3V logic high voltage. Then shorting its logic high output to ground will destroy its output transistor that drives the output high.
I have never used a logic pulser to destroy the output of a logic IC.So the Logic Pulser , does what to the HIGH logic state? is it riding ontop of the High Logic state? since it's not forcing
Then instead of forcing and destroying why don't you allow logic to make the tests? If you want an output to be low then use logic on its inputs so it makes its own output low. If you want an output to be high then use logic on its inputs so it makes its own output high.But the output pin that is driving the input pin is a direct connection , a direct trace
Allow logic to make the tests.How can I force an input when there is a direct connection to the output pin that is driving it? I don't want to lift pins or cut traces
Because then you overload and burn out the transistor that is trying to make the output stay low. Why don't you understand???If the TTL output is LOW , why can't i force it to a HIGH logic state?
because heating is voltage times current. The output is forced high so the output transistor has the full voltage across it instead of the normal very small voltage (logic low voltage) AND it has high current from the forcing. So the output transistor gets very hot and burns out.The TTL output is low close to zero voltage, what's the problem with me injecting a HIGH logic voltage level from an external power supply
The datasheet does not say what the maximum output current is when it is high and you force it low. It is probably a very high current.It's the same thing as if the TTL output switch to a HIGH logic voltage level right?
You do not make sense. How can the output voltage be small when you are forcing it to be a high voltage?Or are saying when I inject a HIGH logic voltage level onto the TTL output when the TTL output is low ( close to zero volts ) it will damage the TTL output even tho it's a LOW state close to zero volts?
The output current increases because when you force a low output to be high then the output transistor inside the IC is fighting to stay low but it is forced to be high. Logic low and logic high levels are voltages, not currents. A logic low output current of a TTL IC has a maximum allowed amount of 16mA.How can the current be HIGH when the output pin is LOW logic level? that doesn't make since
You don't understand simple electronics and you don't understand ordinary English.Are you saying when I inject a HIGH state on to the output pin it SINK's the current from the external power supply into the output pin and destroys it?
I said that ordinary TTL logic gates have TWO output transistors. One pulls up the output and the other pulls down the output.You said that tho ordinary TTL logic gates don't have an output transistor, so how an i Destroy the output transistor when there isn't any? that's the point of the pull up resistor
Then instead of forcing and destroying why don't you allow logic to make the tests? If you want an output to be low then use logic on its inputs so it makes its own output low. If you want an output to be high then use logic on its inputs so it makes its own output high.
You know the truth table of the gate so you know that the inputs have that condition and you confirm it by measuring the inputs but the output of that gate does not go high.
Then either that gate is defective (probably) or the following gate's input is shorted to ground (unlikely).