Which of the figure for DMA block diagram is correct? I am confused

[shivajikobardan]

First figure-:

**broken link removed**

Second figure-:
**broken link removed**

My confusion-:
in first figure how does data transfer between I/O and memory occurs? Neither IO can send data nor receive data according to that figure as it is not connected to memory.
(Does it go the DMAC route??) I am still confused because I can't digest those 3 lines from DMAC and IO device. I think there must be only 2 lines there DREQ from io to dmac and DACK from dmac to io.
in the second figure, why there is way from memory to io only but what if I want to transfer data from io to memory? how do we do that?

 

[rjenkinsgb]

In the first diagram, the three lines will be address, data and control busses.

There are various schemes, but in some way a DMA controller has to intercept and be able to override the address, I/O and memory control signals, to be able to do transfers outside of the CPU programmed instructions - but still pass the control lines through for normal CPU access.

The data bus may be common and used directly, eg. by the DMA controller commanding a memory read and I/O write (or vice versa) while the CPU is not accessing the data bus, or it could work as a proxy and eg. do synchronous accesses to memory and separate async access to the I/O device, storing and transferring a word in whichever way is needed.