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That's so the maximum symmetrical output swing can go from near Vcc to near ground without clipping.....................
Why all the electronic books say that for symmetric VCE must = VCC/2?
is that approximation?
Thank you Mike
Why all the electronic books say that for symmetric VCE must = VCC/2?
Here is a sim of a gain of 20 amp. The sim is run with different values of R3; where the lt. blue trace seems to have the lowest distortion (R3=90K).
Note the plot of V(c)-V(e). The lt blue (R3=90K) trace starts out at 5V (half V(cc)), so it looks like the textbook is right.
Did you doubt the text book? What did the text book say about the peak amplitude at V(c) before serious distortion appears there? Only someone who didn't care about distortion would operate this amplifier with an amplitude approaching these levels. At lower amplitudes, the bias point is less critical...
There is no sim
OK
another question: If I have two designs (like the above one) which
are the same except that one designed around IC=0.1 mA and the other has IC =10mA
I know that the first maintains the battery and has larger input impedance and larger output impedance than the second.
are there other differences between?
thanks
Yes, of course. The gain of the stage is prop. to Ic (because the transconductance gm is related to Ic).
However, if the gain is set by having an unbypassed emitter resistor such as in the sim, this matters not.
Can I understand from your words that the design with a small IC is better for a small signal common emitter bjt?
The best view for the linearity is to see a 'perfect' triangle of the same amplitude very near to the actual output. That immediately shows any curve (non linearity) very clearly.