What is the problem?

Status
Not open for further replies.
ericgibbs, the OP needed to have a divide by 2 counter by looping the out put to the input, where he struggled.
hi,
Its not my circuit, its GaryB's. the OP said it did not work, it works as a RS latch as Gary drew it, thats all I checked.
I cannot understand why the OP has to use a 74LS00, when a D F/F will do what he wants.???

Regards
 
OP in his post#1 stated...
Example is this. I connect its Q' to its D input. Q is supposed to be 0 then 1 then 0....but it works indefinitely. As if it is in undefined state What causes this? How can I fix it?

Indirectly he wanted to make a divide by 2 counter. i suggested to try the one i posted in #11. i don't know which one he said not working..
 
OP in his post#1 stated...


Indirectly he wanted to make a divide by 2 counter. i suggested to try the one i posted in #11. i don't know which one he said not working..

hi,
This is what I get with your circuit, I hope I have copied it correctly.
 

Attachments

  • AAesp04.gif
    40.9 KB · Views: 122
for every clock pulse there must be a state change...but in the simulation it takes few clocks, i doubt the caps playing a role?

hi,
If I remove the 'dta input source' , this what I see in simulation.
The 100pF caps are to enable the simulator to give a solution.
 

Attachments

  • AAesp05.gif
    39.7 KB · Views: 119
hi,
If I remove the 'dta input source' , this what I see in simulation.
The 100pF caps are to enable the simulator to give a solution.

of cause it has to be tested without data input source, it seem you have removed the feed back from Q' too?. try if you have a step by step simulation to see how data changes with eevry clock pulse raising & lowering.
 
of cause it has to be tested without data input source, it seem you have removed the feed back from Q' too?. try if you have a step by step simulation to see how data changes with eevry clock pulse raising & lowering.

hi,
I dont see any feed back on your circuit from Q, the simulation circuit is the same as your post.?? #11
 
Last edited:
on your post #23 its shown correctly, q2 & data are connected (feed back), i meant the same.

I see, the 'dta' source was just a trial, it should not have been shown on that #23 post.

Do you have LTspice on your PC, its a free download.??
I would be pleased to post my asc file for the circuit, so that you can experiment.
 
Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…