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Verilog Processor

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Sling

New Member
Trying to use verilog to design a 4-instruction 16-bit processor including instruction registry, data memory, ALU, controller, accumulator and mux modules.

I can write each individual module ok I think, it's putting it all together that I'm having problems with. It doesn't seem to be covered anywhere in any of the books I have.

Should I put the logic in a seperate module or keep it in the top-level entity? Do I need wires in the top-level entity? Shouldn't variables specified as outputs be automatically defaulted to wires, but how come in the few examples I come across (which never seem to actually work themselves) wires are specified???

Just need to know the general approach to take. Please help!
 
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Sling

New Member
I'm starting to think this is one of those things that noone tells anyone else because if everyone knew how easy the job is once you know how, anyone could do it... But if noone tells you how to do it, there's no way to just guess it. :(
 

BrownOut

Banned
Put the modules into seperate files. Outputs can be either wires or registers. Any signal you have that is assigned in sequential blocks need to be registers, but they can be connected at the module's port. Don't declare any input port signals as registers. At the top level, connected the signals using wires. You have no need for registers at the top level. In your simulator, add all of the files that make up your processor, the order of the of the files in your tools does not normally matter in verilog.

This information is widely discussed in text books. Look up "structural" verilog for more information about top level design.
 
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Sling

New Member
Thanks for the reply Brownout. I've done everything you say there but getting a load of error messages from the Quartus II compilation.

Error (10137): Verilog HDL Procedural Assignment error at comp4.v(54): object "Write" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(55): object "Read" on left-hand side of assignment must have a variable data type
Error (10161): Verilog HDL error at comp4.v(60): object "Data_Address" is not declared
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(61): object "Dm_write" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(62): object "Dm_read" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(64): object "Write" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(65): object "Read" on left-hand side of assignment must have a variable data type
Error (10161): Verilog HDL error at comp4.v(70): object "Data_Address" is not declared
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(71): object "Read" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(72): object "Write" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(73): object "Y_sel" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(74): object "Dm_write" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(75): object "Dm_read" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(80): object "Read" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(81): object "Y_sel" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(82): object "Write" on left-hand side of assignment must have a variable data type
Error (10161): Verilog HDL error at comp4.v(83): object "Data_Address" is not declared
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(84): object "Dm_write" on left-hand side of assignment must have a variable data type
Error (10137): Verilog HDL Procedural Assignment error at comp4.v(85): object "Dm_read" on left-hand side of assignment must have a variable data type
...
Error: Quartus II Full Compilation was unsuccessful. 21 errors, 0 warnings



All of the data-paths have wires allocated in the top-level entity. I don't understand it.

There are some basic examples in my books but nothing that covers a processor. I'm not even sure if the top-level entity should have the clock as an input (apart from that it is completely self-contained) even though when I try experimenting, it doesn't work or without without due to error messages. :confused:
 

BrownOut

Banned
Your errors appear to be in the sub module, and not the top-level structural file. I don't know how you've declared your signals, so I can't tell you how to fix your errors. Also, you can use most tools to check your individual modules for errors before attempting to compile the entire design, and I would strongly suggest you do that. BTW, there isn't anything special about making a processor. It's exactly the same as the examples in your book. I've made several processor in verilog and vhdl.
 
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BrownOut

Banned
Example of what? My designs are multiple modules. I don't have examples available in verilog anyway. I have vhdl and system c on my home computer.
 

Sling

New Member
Ok well I found the cause of the '"Data_Address" is not declared' related error messages - in some of the code it had a lower-case a for address.

So now I just have the 'object "..." on left-hand side of assignment must have a variable data type' messages. The modules all seem to be programmed perfectly now so I simply haven't got the foggiest idea what could be wrong with it.
 

BrownOut

Banned
If the modules were programmed perfectly, you would not be getting an error message. How are you declaring these signals? How are you assigning them?
 

Sling

New Member
Well I go over them again and again and can't find anything wrong - it has to be the structure of the code ... I enclosed the full code so you can see. I've got a feeling I've got the structure totally wrong. :(
 

Attachments

  • verilog processor.txt
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BrownOut

Banned
Well, for one thing, your compiler wants you do declare your port signals. Example:

module controller(clk, Data, PC, Data_address, Dm_write, Dm_read, Aconst, D_sel, Y_sel, Read, Write, Al_cntrl);

input [11:0] Data;
input clk;
output [3:0] PC, Al_cntrl;
output [3:0] Data_address;
output [7:0] Aconst;
output [1:0] D_sel;
output Dm_write, Dm_read, Y_sel, Read, Write

reg Dm_write;
reg Dm_read;
reg Y_sel;
reg Read;
reg Write;
...
 
Last edited:

Sling

New Member
OK thanks for pointing that out. I went over the code and made sure that even the 1-bit ports were reg for the outputs. So now that's fixed I got an avalanche of new error messages. I'm starting to get a bit desperate here. Willing to pay money for help on this. :(

Warning (10230): Verilog HDL assignment warning at comp4.v(126): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(127): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(128): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(129): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(130): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(131): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(132): truncated value with size 12 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(133): truncated value with size 12 to match size of target (4)
Warning (10030): Net "Inst_mem.data_a[3]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.data_a[2]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.data_a[1]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.data_a[0]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.waddr_a[2]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.waddr_a[1]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.waddr_a[0]" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Warning (10030): Net "Inst_mem.we_a" at comp4.v(122) has no driver or initial value, using a default initial value '0'
Info: Elaborating entity "data_mem" for hierarchy "data_mem:data_mem1"
Warning (10235): Verilog HDL Always Construct warning at comp4.v(163): variable "Data_in" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at comp4.v(163): truncated value with size 8 to match size of target (4)
Warning (10235): Verilog HDL Always Construct warning at comp4.v(163): variable "Data_address" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(165): variable "Data_address" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at comp4.v(160): inferring latch(es) for variable "Data_out", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "Data_out[0]" at comp4.v(160)
Info (10041): Inferred latch for "Data_out[1]" at comp4.v(160)
Info (10041): Inferred latch for "Data_out[2]" at comp4.v(160)
Info (10041): Inferred latch for "Data_out[3]" at comp4.v(160)
Info: Elaborating entity "mux_3_to_1" for hierarchy "mux_3_to_1:mux_3_to_11"
Warning (10235): Verilog HDL Always Construct warning at comp4.v(187): variable "Aconst" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(189): variable "Data_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(191): variable "Alu_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at comp4.v(184): inferring latch(es) for variable "Mux_out", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "Mux_out[0]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[1]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[2]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[3]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[4]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[5]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[6]" at comp4.v(184)
Info (10041): Inferred latch for "Mux_out[7]" at comp4.v(184)
Info: Elaborating entity "A_mux_Accum" for hierarchy "A_mux_Accum:A_mux_Accum1"
Warning (10235): Verilog HDL Always Construct warning at comp4.v(214): variable "A_Mux" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(215): variable "x" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(217): variable "A_Mux" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(219): variable "Mux_out" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at comp4.v(210): inferring latch(es) for variable "x", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at comp4.v(210): inferring latch(es) for variable "y", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at comp4.v(210): inferring latch(es) for variable "A_Mux", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "A_Mux[0]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[1]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[2]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[3]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[4]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[5]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[6]" at comp4.v(210)
Info (10041): Inferred latch for "A_Mux[7]" at comp4.v(210)
Info (10041): Inferred latch for "y[0]" at comp4.v(210)
Info (10041): Inferred latch for "y[1]" at comp4.v(210)
Info (10041): Inferred latch for "y[2]" at comp4.v(210)
Info (10041): Inferred latch for "y[3]" at comp4.v(210)
Info (10041): Inferred latch for "y[4]" at comp4.v(210)
Info (10041): Inferred latch for "y[5]" at comp4.v(210)
Info (10041): Inferred latch for "y[6]" at comp4.v(210)
Info (10041): Inferred latch for "y[7]" at comp4.v(210)
Info (10041): Inferred latch for "x[0]" at comp4.v(210)
Info (10041): Inferred latch for "x[1]" at comp4.v(210)
Info (10041): Inferred latch for "x[2]" at comp4.v(210)
Info (10041): Inferred latch for "x[3]" at comp4.v(210)
Info (10041): Inferred latch for "x[4]" at comp4.v(210)
Info (10041): Inferred latch for "x[5]" at comp4.v(210)
Info (10041): Inferred latch for "x[6]" at comp4.v(210)
Info (10041): Inferred latch for "x[7]" at comp4.v(210)
Info: Elaborating entity "alu" for hierarchy "alu:alu1"
Warning (10235): Verilog HDL Always Construct warning at comp4.v(244): variable "x" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at comp4.v(244): variable "y" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at comp4.v(241): inferring latch(es) for variable "Alu_out", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "Alu_out[0]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[1]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[2]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[3]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[4]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[5]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[6]" at comp4.v(241)
Info (10041): Inferred latch for "Alu_out[7]" at comp4.v(241)
Info: Elaborating entity "controller" for hierarchy "controller:controller1"
Warning (10230): Verilog HDL assignment warning at comp4.v(57): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(67): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(77): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at comp4.v(104): truncated value with size 32 to match size of target (4)
Warning: Net is missing source, defaulting to GND
Warning (12110): Net "Data_out[7]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[6]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[5]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[4]" is missing source, defaulting to GND
Warning: Net is missing source, defaulting to GND
Warning (12110): Net "Data_out[7]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[6]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[5]" is missing source, defaulting to GND
Warning (12110): Net "Data_out[4]" is missing source, defaulting to GND
...
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 50 warnings
 

BrownOut

Banned
First of all, breath..... you may not need to worry about warnings, and certainly not about info. The last message says you have only 3 errors. What are they?
 
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Sling

New Member
Lol yeah recovering from the flu atm and been working on this for a few days now... *sigh*

So now I changed the dimensions of one of the register sets (damn!) and just getting :

Error (10251): Verilog HDL error at comp4.v(130): index 4 cannot fall outside the declared range [3:0] for dimension 0 of array "Inst_mem"
Error: Can't elaborate user hierarchy "instruction_mem:instruction_mem1"
...
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings


*edit this is for the line :

Inst_mem[4] <= 12'b010000000001; //ADD accumulator to Data_Address=4'b0001, store in accumulator
 
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BrownOut

Banned
Compilers do array boundary checking. Make sure you don't go over a bound of any array. If you've programed in C, you're not used to seeing boundary checking.
 

Sling

New Member
The registry dimensions are correct now but getting another flood of warning messages, and an error message saying 'Error: Can't synthesize current design -- Top partition does not contain any logic'.
 

BrownOut

Banned
I edited this post because I thought your top module was empty. Glad it complied. Now you need to simulate it.
 
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Sling

New Member
Yeah thanks a lot for the help BrownOut. I'm frankly scared to simulate it right now lol. I'll be gobsmacked if it works as intended straight away but at least I'll be able to use the simulator results to continue debugging - I'm on the right path now I think.

Thanks again!
 
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