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# -ve signal & digital ckt.s

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#### leonidus

##### New Member
Digital ckt.s deal with 1's & 0's. We use positive logic system, generally, i.e. signal in range 3.5 to 5 as high(1) & in range 0 to 1 as low(0). Now what if I want to use negative signals with digital circuits?
Will someone pls. explain me how these things work?

Hi,

First look at a positive logic AND gate truth table:

(this is arranged as inputA,inputB,outputC)
AND GATE
0 0 0
0 1 0
1 0 0
1 1 1

Now note that we can read this two ways...

Way 1:
A '1' on BOTH inputs produces a '1' on the output, thus we say that
'1' AND '1' equals a '1' so it's an AND gate.

Way 2:
A '0' on EITHER input produces a '0' on the output, thus we say that
'0' OR '0' equals a '0' so it's an OR gate, but because we looked at zeros this
time we say that it is 'negative' logic.

Thus, a positive logic AND gate is a negative logic OR gate.
An example would be the 7400 series gate package, which has four
AND gates (they are called by their positive logic name but can still be
used for negative logic).
Often systems will use gates both ways.

Thanks for that explanation. But, I already knew that. I want to get to know how these gates or any other digital ckt. will work if I apply a negative signal
e.g.: (-4)V signal as input.

Thanks for that explanation. But, I already knew that. I want to get to know how these gates or any other digital ckt. will work if I apply a negative signal
e.g.: (-4)V signal as input.

You don't - and why would you want to?.

As Nigel says - you don't. The voltage you apply to the inputs is typically the base voltage of a transistor, so what will happen is that as you drop the voltage from +V towards 0V the transistor will switch off, and as you continue to decrease the voltage the transistor will stay off until the voltage exceeds some breakdown limit, at which stage anything could happen. If you want to redefine 0V as high and -V as low then that's different; you could do that and you're effectively then just offsetting the whole circuit by some voltage and there will be no net difference; 0V will then be '1' and -V will be '0', and 0V AND 0V -> 0V, 1V AND -V -> -V and so on.

So to get a meaningful answer you need to answer the "why" questin. What are you trying to do?

Once upon a time before TTL, there was DTL that used GND and -3V for logic levels. There was also ECL that used a -5.2V supply and had logic levels in the linear region. I've even seen 4000 series CMOS chips used between -800 V and -810V in place ov VCC and GND.

The absolute levels make no difference whatsoever.

Thanks to all!!!
I want to make a small bot without using a µp. I thought using a digital ckt.. The following table defines its functions:-
SENSORS MOTOR
O/P CONNECTIONS WHERE:-
SL SR L+ L- R+ R- 0:SENSOR PRODUCES NO O/P
0 0 + - + - 1:SENSOR PRODUCES O/P
0 1 - + + - L:LEFT R:RIGHT
1 0 + - - + +: POSITIVE VOLTAGE
1 1 + - - + -: NEGATIVE VOLTAGE

So, I made a truth table depending on above condn.s. In that I took +:1,-:0.
That's the reason.

I suggest you rethink your design totally from scratch - you shouldn't have any negative supply, so you can't have any negative voltages anyway.

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