This is the sort of early experiments one tries before learning of the
misteaks of asynchronous counter metastable glitches.
The divide by 33 approach given indeed works by any approach of
analog AND'ing to Reset the counter long before Carry Out is reached. (
Reminds me of a company in Montreal whose stock rose faster than Bitcoin invented a minutia hack for 3D finger authentication as he coined it "ANALOGIC" I was invited to RFQ quote on it, but it was not rocket science and not good authentication then the stock later tanked to $0 in 1 day.)
The pulse height of the analog Reset voltage and its PW50 or 50% peak pulse width depends on how long it takes for any gated output used to be "cleared".
This gave me the idea to make a
useless fraction-N synthesizer using a capacitor on Reset as the CD4xxx gates already have high output resistance, making this a low pass filter.
The logic proposed in this question indeed counts 33 cycles by waiting the rising edge or half cycles of /2 and /64 counters of Q1 and Q6 for (2^1)/2 + (2^6)/2 binary counts to create a metastable Reset pulse = 1 + 32. Now by loading the Reset with more input capacitance, we can delay the Reset by counting more Q1 pulses until it reaches 2.5V or whatever the Reset threshold is for the IC.
Then we have a multiplier,
m and a divider,
n integer to create many more frequencies
f (reset) = multiplier/ divider * f
clk = where the multiplier m is almost = fin/Tau for Tau = RC filter depending on the threshold tolerance for Reset.
f =m / (2^n-1) +1
Qn output labels using the binary sequence asynch. counters of the '4024'
Those who don't mind the different ways of labeling binary counter outputs won't mind the different ways of numbering compatible connector pins with multiple rows.