totem-pole and TTL inverter

[PG1995]

Hi,

Could you please help me with the queries below? Thank you.

Question 1:
I believe that the words pull-up/pull-up network and push-pull network are synonymous in the context of circuits.

It is my understanding that when the word pull-up/pull-down is used, it refers to combination of a resistor and switch such as this one. Such a combination is used to pull the output voltage toward ground or toward the supply voltage; in other words low and high.

The totem-pole circuit also does the same thing, in my opinion, making the output low or high but its use is mostly restricted to turning on/off of FET transistors.

You can see here four circuits and all of them look different from each other considering the layout of components but function-wise they are pretty much the same in the context of given circuit.

Do I have it correct?

Sources:
Circuit #1 and #2 were taken from this webpage.
Circuit #3 is from an MPPT circuit.
Circuit #4 was taken from here.


Please have a look here.

Question 2:
Does this mean that when there is a negative spike at the input, i.e. when the voltage goes below the ground level temporarily, the current flows from ground terminal through D1 to the input? This way current wouldn't flow through Q1 transistor.

Question 3:
It says Vcc=5V but wouldn't it then require HIGH to be greater than 5V if the base emitter junction of Q1 transistor is to be reverse biased.

Question 4:
How are these voltages, 2.1V, 1.4V, and 0.7V calculated? They add up to 4.2V and not to 5V. Perhaps, the author is just trying clarify a point without making an exact calculation.

Thanks a lot!

 

[AnalogKid]

Q1: No. Most of your statements of what you believe and understand are incorrect.

Traditionally, a push-pull output stage is two transistors in series with the load attached between them. One transistor sources current into the load (push) and the other transistor sinks current from the load (pull). They never are on at the same time (intentionally). Pull up and/or pull down are not synonymous. Totem-pole is.

Your image of a switch and a resistor are a switch with a pull up resistor. This is not a push-pull circuit.

Q2: Yes.

Q3: No. Q1's be junction does not have to be fully reverse biased, just enough to stop Q1 from conducting. for a theoretically perfect transistor, this occurs when Vbe is anything less than 0.6V.

ak

 

[Diver300]

1) I have understood "push-pull" to imply that there are active devices driving the circuit high and low, This can be two devices of the same polarity driving though a centre-tapped transformer. Pull up or pull down are not push-pull as they do not have two active devices.

2) Yes, it is very common to have a diode like that to protect the devices from negative voltages.

3) No. Current will flow though R1 to the base of Q2, so there will be a considerable voltage drop in R1, resulting in the base of Q2 being far less than 5 V, so reverse biasing the base-emitter junction will only need about 3 V. Of course, if the base-emitter voltage of Q1 is less than about 0.7 V, no current will flow, so the rest of the circuit will behave as though the base-emitter junction is reverse biased.

4) The voltages 2.1V, 1.4V, and 0.7V are voltages above the 0 V rail. They are just 3, 2 and 1 times a typical silicon diode voltage. When the input is high, Q2 and Q3 are both turned on, so each has a base-emitter voltage of 0.7 V. As the emitter of Q3 is at ground, that makes its base voltage about 0.7 V. Q2's emitter is at 0.7 V, so it's base is at 0.7 + 0. 7 = 1.4 V. Q1 has got it's base-collector junction forward biased in that condition, so that junction voltage is also 0.7 V. As the collector of Q1 is connected to the base of Q2, which is at 1.4 V, the base of Q1 is at 1.4 + 0.7 V = 2.1 V, leaving 5 V - 2.1 V = 2.9 V across R1. The base-emitter junction of Q1 will conduct when the voltage on the input is less than about 1.4 V.

The typical characteristics can be seen here

 

[PG1995]

Thank you!

But I had forgotten to include the main file for Question #1. I have also edited the original post now.

 

[summitville]

Hi,

Question 1:
I believe that the words pull-up/pull-up network and push-pull network are synonymous in the context of circuits.

It is my understanding that when the word pull-up/pull-down is used, it refers to combination of a resistor and switch such as this one. Such a combination is used to pull the output voltage toward ground or toward the supply voltage; in other words low and high.

The totem-pole circuit also does the same thing, in my opinion, making the output low or high but its use is mostly restricted to turning on/off of FET transistors.

You can see here four circuits and all of them look different from each other considering the layout of components but function-wise they are pretty much the same in the context of given circuit.

Do I have it correct?

1) Totem-Pole output is Push-Pull - meaning there are two transistors in the output. One transistor actively pulls the Output High, alternatively the other transistor actively pulls the Output Low. If you don't exceed the sink current or source current then the output voltage is guaranteed. Typically, only one output directly feeds, one or more inputs.

2) Open Collector outputs typically use Pull-Up Resistors. Many outputs can be OR'd Low Active. The Pull-Up Resistor limits the Source Current.

3) Line Driver outputs typically use Pull-Down Resistors. Many outputs can be OR'd Active High. The Pull-Down Resistor limits the Sink Current.

TTL-OUTPUTS

While the three (3) types of outputs are similar, they are quite different, and are not easily interchangeable.

 

[summitville]

Question 2:
Does this mean that when there is a negative spike at the input, i.e. when the voltage goes below the ground level temporarily, the current flows from ground terminal through D1 to the input? This way current wouldn't flow through Q1 transistor.

Yes, it is true that a negative voltage on the input pin will cause current to flow in diode D1.
But no, your assumption regarding Q1 turning OFF is incorrect. Current will continue to flow through Q1.

 

[PG1995]

Thank you, AnalogKid, Diver300, summitville.

Re: Question 1

Q1: No. Most of your statements of what you believe and understand are incorrect.

Traditionally, a push-pull output stage is two transistors in series with the load attached between them. One transistor sources current into the load (push) and the other transistor sinks current from the load (pull). They never are on at the same time (intentionally). Pull up and/or pull down are not synonymous. Totem-pole is.

Your image of a switch and a resistor are a switch with a pull up resistor. This is not a push-pull circuit.

I believe that you are saying that pull-up and/or pull down networks are not synonymous with push-pull but the word totem-pole is interchangeable with push-pull.

You said that a push-pull output stage is two transistors in series with the load attached between them. So, I believe that's the main characteristic to identify a push-pull or totem-pole. All of the shown circuits here could be identified as totem pole where the load is attached between the two transistors though how other transistor(s) or resistors are connected to those two transistor differ from one circuit to another. I believe that how other components are connected to the two transistors is dictated by other requirements of a given circuit.

You are correct that the image is of a pull up resistor. This is pull down resistor.

Re: Question 2

Yes, it is true that a negative voltage on the input pin will cause current to flow in diode D1.
But no, your assumption regarding Q1 turning OFF is incorrect. Current will continue to flow through Q1.

Yes, a limited current will also flow through R1 and Q1 as a result of negative spike but it won't damage Q1 because most of the current would flow through diode D1. This is the circuit being discussed.

Re: Question 3

Q3: No. Q1's be junction does not have to be fully reverse biased, just enough to stop Q1 from conducting. for a theoretically perfect transistor, this occurs when Vbe is anything less than 0.6V.

This is the circuit being discussed. The base emitter junction of transistor Q1 should be reverse biased when input is HIGH. Let's say HIGH=4V. Wouldn't it make BE junction forward biased because Vbase is 5V? Yes, it might be reverse biased if HIGH=4.5V instead.

Re: Question 4

4) The voltages 2.1V, 1.4V, and 0.7V are voltages above the 0 V rail. They are just 3, 2 and 1 times a typical silicon diode voltage. When the input is high, Q2 and Q3 are both turned on, so each has a base-emitter voltage of 0.7 V. As the emitter of Q3 is at ground, that makes its base voltage about 0.7 V. Q2's emitter is at 0.7 V, so it's base is at 0.7 + 0. 7 = 1.4 V. Q1 has got it's base-collector junction forward biased in that condition, so that junction voltage is also 0.7 V. As the collector of Q1 is connected to the base of Q2, which is at 1.4 V, the base of Q1 is at 1.4 + 0.7 V = 2.1 V, leaving 5 V - 2.1 V = 2.9 V across R1. The base-emitter junction of Q1 will conduct when the voltage on the input is less than about 1.4 V.

I'm sorry but I'm confused. This is the circuit being discussed. The base-emitter junction would get forward biased even when the voltage on input is 3V because Vb - Ve = 5-3=2V which is greater than 0.7V.

Thank you for the help and your time!

 

[Diver300]

Thank you, AnalogKid, Diver300, summitville.


Re: Question 4

1) I have understood "push-pull" to imply that there are active devices driving the circuit high and low, This can be two devices of the same polarity driving though a centre-tapped transformer. Pull up or pull down are not push-pull as they do not have two active devices.

2) Yes, it is very common to have a diode like that to protect the devices from negative voltages.

3) No. Current will flow though R1 to the base of Q2, so there will be a considerable voltage drop in R1, resulting in the base of Q2 being far less than 5 V, so reverse biasing the base-emitter junction will only need about 3 V. Of course, if the base-emitter voltage of Q1 is less than about 0.7 V, no current will flow, so the rest of the circuit will behave as though the base-emitter junction is reverse biased.

4) The voltages 2.1V, 1.4V, and 0.7V are voltages above the 0 V rail. They are just 3, 2 and 1 times a typical silicon diode voltage. When the input is high, Q2 and Q3 are both turned on, so each has a base-emitter voltage of 0.7 V. As the emitter of Q3 is at ground, that makes its base voltage about 0.7 V. Q2's emitter is at 0.7 V, so it's base is at 0.7 + 0. 7 = 1.4 V. Q1 has got it's base-collector junction forward biased in that condition, so that junction voltage is also 0.7 V. As the collector of Q1 is connected to the base of Q2, which is at 1.4 V, the base of Q1 is at 1.4 + 0.7 V = 2.1 V, leaving 5 V - 2.1 V = 2.9 V across R1. The base-emitter junction of Q1 will conduct when the voltage on the input is less than about 1.4 V.

The typical characteristics can be seen here

I'm sorry but I'm confused. This is the circuit being discussed. The base-emitter junction would get forward biased even when the voltage on input is 3V because Vb - Ve = 5-3=2V which is greater than 0.7V.

Thank you for the help and your time!

There will be current flowing in R1, so there will be a voltage across R1. The top end of R1 is at 5 V, so the bottom end of R1 will be at less than 5 V.

In fact, the voltage at the bottom end of R1 will be about 2.1 V. The amount of current in R1 is controlled by the value of R1, which is typically 4 kOhm, so around 0.75 mA will flow. If we calculate Vbe, it is given by Vb - Ve = 2.1 - 3 = -0.9 V, which is less (as in more negative) than 0.7 V

The 2.1 V is made up of three PN juctions, each with a voltage of about 0.7 V. The three PN junctions are:-
Base - Emitter of Q3
Base - Emitter of Q2
Base - Collector of Q1

The TTL input circuit is slightly odd in that the Base - Collector junction of Q1 is forward biased in normal operation, when the input is high. That is unusual for any transistor circuit, as most will always have the Base - Collector junction reverse biased. However, if you take a diode tester to any normal NPN transistor, there will be about 0.7 V drop from the Base to either the Emitter or the Collector. Q1 is no different.

 

[summitville]

Re: Question 2
Yes, a limited current will also flow through R1 and Q1 as a result of negative spike but it won't damage Q1 because most of the current would flow through diode D1. This is the circuit being discussed.

Yes, I now agree with your latest summary of a Negative Pulse on the Input Pin:

When a Negative Pulse occurs on the Input Pin ...
1) Nearly the same amount of current will continue to flow through Q1 = ON vs when the Input Pin is typically grounded.
2) As the Input Pin goes more negative, an increasing amount of current will now flow through D1.

Diode D1 can protect Transistor Q1, but only up to point and then D1 will fail, either Short or Open.

 

[summitville]

Re: Question 4

I'm sorry but I'm confused. This is the circuit being discussed. The base-emitter junction would get forward biased even when the voltage on input is 3V because Vb - Ve = 5-3=2V which is greater than 0.7V.

Look at the voltage on the Base of Q1 in your drawing.
Your own drawing states the voltage at the Base of Q1 = 2.1 Volts, not 5 Volts

 

[PG1995]

Thank you for your help, Diver300 and summitville.

I was waiting for AnalogKid 's reply to my follow-up on Question 1 before I ask another related question but anyway I will proceed.

Please have a look here.

Circuit #1:
If Vcc is greater than the drive voltage, when drive voltage is high Q1 turns on. The current starts flowing into the gate. N-channel enhacement FET's gate acts like a capacitor.

The current starts decreasing as the gate charges up. Suppose that when the gate starts getting charged up, voltage drop across Rgate is 3V; the left terminal is at 3V and right terminal at 0V. But as the gate is charged voltage on the right terminal, x V of Rgate starts building up and voltage drop (3-x) decreases. The transistor would stop conducting when 3-x=0 or when voltage drop across Rgate becomes zero. At this Vbe for Q1 is zero too assuming drive voltage is 3V. It means that the gate won't get fully charged up. A partially charged gate won't fully open up FET channel and it would offer significant resistance to the current flow.

In this case like when Vcc is greater than the drive voltage, the operation won't be affected for LOW drive voltage. The gate would fully discharge through Q2 for LOW drive voltage.

Is my understanding correct?

Circuit #2:
I'm going to ignore R5 resistor as if it's not there because I cannot make any sense of the circuit by its inclusion.

I understand that what I'm saying below is not correct but it will let you see where I'm going wrong.

When drive voltage is LOW, Q1 transistor won't conduct. It will turn on Q3 and the gate will be charged up.

When drive voltage is HIGH, Q1 will conduct and the current would follow easier path to the ground through R1 and Q1. PNP Q2 will also conduct to get the gate discharged because the node "A" would be at lower potential compared to the gate's voltage.

Please help me with this circuit because I don't get it at all. It looks like Q1 will always conduct even when drive voltage is LOW because it's connected Vcc through R5.



The following is a note to self so you can ignore it.

Let's restate Question 4.

In FIGURE 15-28 (a) below the circuit operation is shown for HIGH input. My main confusion was about the value of minimum voltage for HIGH for the shown operation in the figure, or what the value of minimum voltage at input should be to get base-emitter junction forward biased.

In the figure, we can see that the voltage at base of Q1 is 2.1 V with reference to the ground and in the posts above Diver300 has explained the reason for this value. This 2.1 V voltage makes the base-collector junction forward biased which is important for HIGH input operation.

Let's start when the input is LOW, i.e. 0 V. For LOW, the current flows through R1 and Q1. For LOW, base-emitter junction of Q1 is forward biased.

Now suppose you start raising the voltage at input toward HIGH. In case of HIGH, base-emitter junction of Q1 should get reverse biased.

When input is 1 V, the voltage at base should be at least 1.7 V (assuming junction voltage to be 0.7 V) to make base-emitter junction forward biased. The base-emitter junction would still be forward biased and output would be LOW.

When input is 2 V, the voltage at base should be at least 2.7 V (assuming junction voltage to be 0.7 V) to make base-emitter junction forward biased.

When input is 1.6 V, the voltage at base should be at least 2.3 V to make base-emitter junction forward biased. But as soon as voltage at the base is 2.1 V, the current has an alternative path through base-collector junction of Q1.

The base-emitter junction would only get forward biased when the required base voltage is less than 2.1 V. In other words, when voltage is less than 2.1 - 0.7 = 1.4 V as Diver300 already stated above.

 

[summitville]

Thank you for your help, Diver300 and summitville.

I was waiting for AnalogKid 's reply to my follow-up on Question 1 before I ask another related question but anyway I will proceed.

Please have a look here.

Circuit #1:
If Vcc is greater than the drive voltage, when drive voltage is high Q1 turns on. The current starts flowing into the gate. N-channel enhacement FET's gate acts like a capacitor.

The current starts decreasing as the gate charges up. Suppose that when the gate starts getting charged up, voltage drop across Rgate is 3V; the left terminal is at 3V and right terminal at 0V. But as the gate is charged voltage on the right terminal, x V of Rgate starts building up and voltage drop (3-x) decreases. The transistor would stop conducting when 3-x=0 or when voltage drop across Rgate becomes zero. At this Vbe for Q1 is zero too assuming drive voltage is 3V. It means that the gate won't get fully charged up. A partially charged gate won't fully open up FET channel and it would offer significant resistance to the current flow.

In this case like when Vcc is greater than the drive voltage, the operation won't be affected for LOW drive voltage. The gate would fully discharge through Q2 for LOW drive voltage.

Is my understanding correct?

Yes, initially the Voltage drop across Rgate will be large.
Initially the "Gate Current" is = ( "Drive Voltage High" - 0.7 ) / Rgate
and the Gate Current will decrease, as the Gate Voltage rises.
The Gate will "Charge-Up" to nearly what ever the "Drive Voltage High" is.
If the Drive Voltage is too low then YES the Gate Voltage may be too low, too.

 

[summitville]

Circuit #2:
I'm going to ignore R5 resistor as if it's not there because I cannot make any sense of the circuit by its inclusion.

I understand that what I'm saying below is not correct but it will let you see where I'm going wrong.

When drive voltage is LOW, Q1 transistor won't conduct. It will turn on Q3 and the gate will be charged up.

When drive voltage is HIGH, Q1 will conduct and the current would follow easier path to the ground through R1 and Q1. PNP Q2 will also conduct to get the gate discharged because the node "A" would be at lower potential compared to the gate's voltage.

Please help me with this circuit because I don't get it at all. It looks like Q1 will always conduct even when drive voltage is LOW because it's connected Vcc through R5.

R5 is a Pull-Up resistor.
R5 keeps Q1 ON, when there is no input connection.
R5 can by a rather larger value - making it easy for the Driver Device to PULL the Input Pin LOW.

Q1 acts as Voltage Level Shifter circuit and it inverts the logic.
Q1 allows the MOSFET Gate to charge-up to a higher voltage, nearly Vcc, even with a low voltage Drive Signal.

The device that is the "Drive Signal" must be able to pull the Input Pin to (near) Ground - ie a Totem Pole Output or Open Collector.

 

[PG1995]

Thanks a lot, summitville !

R5 keeps Q1 ON, when there is no input connection.

But there is always going to be an input; mostly PWM signal changing between HIGH and LOW. Perhaps, you are saying that even if there is no HIGH input signal present at the base of transistor Q1, the transistor would conduct anyway but the presence of HIGH input signal would make it conduct more current. Assuming what I have already said is correct, for HIGH input Ib increases and now Vce would decrease and more voltage drop would occur across R1 and potential at the node "A" decreases. This will turn off Q3 but possibly will turn on PNP Q2 because node is essentially at ground. The gate discharges.

Once input is LOW, Q1 turns off because current flowing through R5 has ''easier' path to flow to the ground; assuming a BJT is a current controlled device which many people could object to! The voltage at the node "A" increases, Q3 turns and the gate charges to Vcc.

In short:
HIGH input - the gate discharges
LOW input - the gate charges

Do I make any sense?

By the way, what's the role of capacitor? Is it just there to stabilize the voltage by working as a high-pass filter?

Also, I was trying to understand why totem-pole configuration is called so. Is the reason how it looks - a load connected between two transistors Q1 and Q2?

Thank you for the help and time!

 

[summitville]

Thanks a lot, summitville !

But there is always going to be an input; mostly PWM signal changing between HIGH and LOW.

In short:
HIGH input - the gate discharges
LOW input - the gate charges

By the way, what's the role of capacitor? Is it just there to stabilize the voltage by working as a high-pass filter?

Also, I was trying to understand why totem-pole configuration is called so. Is the reason how it looks -
a load connected between two transistors Q1 and Q2?

R5 is a pull-up such that Q1 defaults to ON with NO INPUT = MOSFET is OFF.
R5 may be there to insure that ... on power-up the MOSFET is OFF, until the Drive Signal is active?
It it always best to design the circuit to power up in a "safe" mode.

In short:
HIGH input = Q1 On, Point "A" Low, Q2 On, Gate DIscharged, MOSFET OFF, R4 OFF
LOW input = Q1 Off, Point "A" High, Q3 On, Gate Charged, MOSFET ON, R4 ON

Yes, C4 appears to be a "power supply bypass" capacitor, to keep the initial MOSFET Turn ON from drooping the Rail Voltage too much.

I assume .. Since, the Push-Pull output has "stacked" transistors, it is similar to objects stacked on a Totem Pole?

 

[PG1995]

Thank you, summitville .

Yes, C4 appears to be a "power supply bypass" capacitor, to keep the initial MOSFET Turn ON from drooping the Rail Voltage too much.

Yes, you are right that the capacitor keeps the rail voltage from drooping too much. In other words, turning on/off of FET will create a ripple and in a capacitor the voltage cannot change instantaneously therefore the capacitor functions as a filter, possibly high pass filter, to keep the voltage level steady much like a shock absorber.

I assume .. Since, the Push-Pull output has "stacked" transistors, it is similar to objects stacked on a Totem Pole?

What you said makes more sense.

 

[PG1995]

Hi,

Could you please help me with the questions in this attachment?

Question 1:
What's the purpose of having TTL inverter wih an open-collector output? You still need to attach possibly another transistor at the shown output which would control the 'attached' external circuit. Stating my question another way, why isn't external circuit attached directly to the 'original' TTL inverter?

You can see that in open collector configuration, R3, Q4, and D2 have been removed from the main TTL inverter circuit as is shown below in FIGURE 15-27.

Wikipedia article, https://en.wikipedia.org/wiki/Open_collector#Applications_of_open-collector_devices, says, "Because the pull-up resistor is external and does not need to be connected to the chip supply voltage, a lower or higher voltage than the chip supply voltage can be used instead. (Providing it does not exceed the absolute maximum rating of the chip's output.) Open collector circuits are therefore sometimes used to interface different families of devices that have different operating voltage levels. The open-collector transistor can be rated to withstand a higher voltage than the chip supply voltage. This technique is commonly used by logic circuits operating at 5 V or lower to drive devices such as motors, 12 V relays, 50 V vacuum fluorescent displays, or Nixie tubes requiring more than 100 V."

I have drawn a circuit on left to show you what I understand from Wikipedia's point about a separate supply voltage. I hope I have it right.

I think that the main advantage among many others is that it doesn't load the main inverter circuit which means that the external circuit doesn't derive much of the current from inverter circuit. There is no need for R3, Q4, and D2 because Q3 only needs to be turned on/off. At the same time one can use different supply voltage than the inverter circuit as is shown on the left but the ground should be connected for both supp,y voltages. The same goes for open drain circuit. Do I make sense?

Question 2:
I think that "Rest of CMOS circuit" is a CMOS inverter just like in the case of open-collector TTL, there is a TTL inverter as is referenced here.

 

[Nigel Goodwin]

Question 1:
What's the purpose of having TTL inverter wih an open-collector output? You still need to attach possibly another transistor at the shown output which would control the 'attached' external circuit. Stating my question another way, why isn't external circuit attached directly to the 'original' TTL inverter?

Simply because it give you a much wider array of options, for example you can use a common pullup resistor and OR/NAND a number of gates together, or use a pullup to a higher or lower supply rail to convert to a different voltage output.

 

[PG1995]

Hi,

Could you please help me with the queries below? I'd really appreciate your help!

I was reading about Schottky TTL here and the following statement which is really important confused me, "Most TTL logic is some form of Schottky TTL, which provides a faster switching time by incorporating Schottky diodes to prevent the transistors from going into saturation, thereby decreasing the time for a transistor to turn on or off."

Question 1:
Then, I Googled and stumbled upon this webpage (source: https://electronics.stackexchange.com/questions/116746/schottky-diode-like-bjt-symbol). Based on the information given on webpage, I tried to understand it as follows. In normal operation only one junction, base-emitter, gets forward biased. But when a BJT is in saturation both of its junctions, base-collector and base-emitter, get forward biased. The base voltage remains around 0.7 V in saturation state but when in saturation both collector and emitter are at lower voltage compared to the base. For forward biasing the base voltage must be 0.7 V more than that of either junction. For a Shottky diode to get forward biased the required voltage differential is only 0.3 V compared to 0.7 V of PN junction of a BJT. In the picture below we can see that as soon as collector voltage falls 0.3 V below that of the base, the diode will start conduction which means base-collector can never get forward biased. In other words, saturation can not be reached because you need both junctions to get forward biased.

Do I have it correct?

Question 2:
Please have a look here on this attachment.

As it was said in the referenced webpage in Question 1 above that in an ordinary BJT, the saturation state collector-emitter voltage falls below or equal to 0.2 V. The same is said at many other places too. To me, it means that whenever a BJT is in saturation for whatever amount of collector current for a certain Ib, Vce is going to be around 0.2 V.

In FIGURE 4-10 (b) the saturation occurs at point "B" and the shown voltage for that point is 0.7 V. If this is the saturation point then why is Vce 0.7 V at this point?

Question 3:
Also in FIGURE 4-10 (b) you can see that between points "B" and "C", Ib increases only by a very small degree but the change in Vce is too much. At point "C", Vce(max) happen. If at saturation Vce should be 0.2 V then why does Vce changes so much beyond saturation point, i.e. point "B".

Thank you for your help and time!

Helpful links
1: https://www.quora.com/Which-factor-affect-switching-speed-of-transistor
2: https://learn.sparkfun.com/tutorials/transistors/all

 

[PG1995]

I'm sorry to bumping it prematurely but I'm stuck with this and wanted to get over this soon. Would really appreciate if someone could guide me. Thanks.