Timer circuit conundrum

[iceblue]

Hi all

I've been trying to construct a timer but cant seem to get one to do what I need.

The timer I require needs to accept two inputs, one of them positive, the other negative. Either of these inputs can trigger the timer but if the timer has been triggered and is then triggered by the second input, it needs to start counting from zero again (regardless of whether or not the previous timing period has completed). Both inputs are latched and could change state before or after the timer expires, but the timer must only be active if at least one of the triggers is active. If both triggers become inactive the timer needs to end its timing period.

I initially tried to do this with a 555 but didn't get far. I am trying to avoid using a uP so hopefully somebody can advise me if I could do this using analogue or logic components.

I am studying electrical engineering but am specializing in telecoms, so my electronics knowledge is restricted to the basics. Could somebody please just point me in the right direction? I don't expect a full circuit diagram, just some advice on what would be the best way to do this.

Thanks

 

[k7elp60]

You may want to look at a 74xx123, as it is a dual retriggerable monstable.
The xx means there are several versions like HC, LS etc.

 

[iceblue]

Thanks. But I forgot to mention that it will be running on a 12V supply. Is there a similar chip for 12V or will I have to stick with the 74xx123 and use a 5v supply?

 

[on1aag]

Hi Iceblue,

Try this, it might even work.

on1aag.

 

[iceblue]

Thanks On1aag

That looks like it will do. I will test it as soon as I get a chance!

 

[k7elp60]

Another possible is a CD4528, which is CMOS and will work on 12V.

 

[iceblue]

Thanks guys!