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Test CD4093BCN

Thread starter #1
14 pin CD4093BCN
How do I go about testing this Quad 2-Input NAND Schmitt Trigger
Out of the circuit.
Last edited:


Well-Known Member
For straight logic function, set up a test fixture that powers the IC, and lets you independently make each input high or low.

Then monitor the state of each output as you change the two inputs of each gate through the four possible combinations. Verify that the input/output states match that of a 2 input NAND.

If you want to test the Schmitt trigger function, then you need variable voltage sources for each of the inputs.


Well-Known Member
A signal generator and a scope would help a lot.
The datasheet surely proposes a test circuit.


Well-Known Member
The NAND gate should be TTL, meaning on the TTL level it should get activated/deactivated, you can try only powering it and checking will it give the proper output("5VDC/0VDC") on the proper input.


Also try this:

CMOS gate circuits have input and output signal specifications that are quite different from TTL

dr pepper

Well-Known Member
Most Helpful Member
Have you considered just using a logic probe, or possibly a more advanced but still cheap method like a salae logic analyser.


Well-Known Member
Touch the probe to a known logic LOW. Observe and note what the LED shows.
Touch the probe to a known logic HIGH. Observe and note what the LED shows.
One way to test would be to configure each NAND-gate in a "Gated Oscillator" configuration and measure the frequency on a scope. To measure if the A and B inputs of the NAND-gate are balanced, you can swap the inputs of the "Gated Oscillator" configuration and measure the frequency again. Do this with each NAND gate one at a time using the SAME resistor and capacitor for the "Gated Oscillator" configuration.
Thread starter #14
I bo not have a scope .
But could you send me a circuit diagram for me to understand.
I only have a logic probe and digital multi meter.
Thank you Greg
Datasheet page #4 "Typical Applications: Gated Oscillator"


You need a scope or frequency counter to balance test the inputs and compare results from NAND gate to NAND gate.
There will be slight differences between the A input and the B input, unless the gate has been specifically designed so that both inputs are balanced. (see side note below) You will also see differences between each NAND gate. The differences are expected, but what you need to determine is if the results are within the expected tolerance determined by you.

Note: At National Semiconductor, I designed IC's as a layout engineer for 15 years. One of the things I did was design standard cell libraries for whatever the current process we were targeting was at the time. Standard cell libraries are your basic logic blocks, AND, NAND, OR, XOR, Inverters, etc. To characterize the Standard cells we would measure the actual silicon in a way I describe above. Balancing the inputs are critical for Standard cells used within an IC, but commercialized IC's such as the CD4093BCN, the balancing is not as critical so you could see slight differences between inputs caused by propagation delays in how the NAND gate is designed, oriented on the silicon, or even how the bond wires connect from the silicon die to the leads on the IC.

dr pepper

Well-Known Member
Most Helpful Member
Its a very simple check, but its a start.
If you have a gate configured as an oscillator, probe the gate input that is bypassed to +v to make sure its high, then probe the input and output of the oscillator, if the oscillator frequency is high both the high & low Led will be on as well as the pulse Led on the probe, if the frequency is low less than afew hertz you'll see the high & low Led witch over on the probe.
By 'probe' I mean touch the probe tip of said logic probe to the pins on the chip, from, memory pins 1 & 2 are the inputs and pin 3 is the output for one of the 4 gates, you can also make sure the chip has power by probing the power pins.
To see which pin is what download the datasheet for the 4093.

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