If you look at the Fig. 2 timing diagram on pg. 5 of the data sheet, you can seen that the SI trigger should go high when the clock is low.
It should go low tsu(SI) seconds before the clock goes high (20ns from pg. 2). It should stay high for th(SI) time after the clock goes high, which is 0ns from the data sheet (which means it can go back low as soon as the clock goes high).
Thus the SI trigger can change from low to high on the falling edge of the clock and from high to low on the rising edge. (The SI trigger should be low before the next clock rising edge)
The time between SI pulses should be at least 129 clock pulses.
You could use a counter, a flip-flop, and some gates to do this. You would enable the flip-flop for one clock-pulse every 129 clocks (or more) from the counter. The flip-flop would gate the (inverted) clock for one clock pulse, giving the desired SI pulse.
To understand and design digital circuits you should be able to read a timing diagram. It's hard to understand digital circuit timing otherwise. You might look at "digital timing diagram" in wikipedia or do a google search for more info.
All this make sense?