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Store numbers on flip flop

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wzseow

New Member
I need to implement a counter with count sequence which stores random numbers using verilog and display it on 7 segmentt display. I have no problems in calling the numbers out as a function, but can someone guide me how do I store random numbers using flip flops? It needs to be activated by a "clock".


I have done part of the verilog code, but i know it is wrong because I am not storing any numbers in the flip flop.

Code:
module Q1(KEY1,HEX0);
	
	input [1:0] KEY1;
	output [6:0] HEX0;
	
	assign CLK = KEY1;
	
	shift_reg (CLK,RESET, 0010,Q);
	shift_reg (CLK,RESET, 0001,Q);
	shift_reg (CLK,RESET, 0010,Q);
	shift_reg (CLK,RESET, 0000,Q);
	shift_reg (CLK,RESET, 0001,Q);
	shift_reg (CLK,RESET, 0111,Q);
	shift_reg (CLK,RESET, 0111,Q);
	shift_reg (CLK,RESET, 0011,Q);
	shift_reg (CLK,RESET, 1000,Q);
	shift_reg (CLK,RESET, 1000,Q);
	
endmodule

	
// 4-bit Shift Register with Reset

module shift_reg (CLK, RESET, in, Q);
	
	input CLK, RESET;
	input [3:0] in;
	output [3:0] Q;
	
	reg[3:0] Q;
	

	always@(posedge CLK or posedge RESET)
	begin
	
	if (RESET)
	Q <= 4'b0000;
	else
	Q <= {Q[3:0], in};
	end
	
	display (Q,HEX0);
	endmodule


//*****HEX Module*****////
module display (U,HEX0);

input [0:3] U;
output [6:0] HEX0;

	assign HEX0[0]=(~U[0]&~U[1]&~U[2]&U[3])|(~U[0]&U[1]&~U[2]&~U[3]);
	assign HEX0[1]=(~U[0]&U[1]&~U[2]&U[3])|(~U[0]&U[1]&U[2]&~U[3]);
	assign HEX0[2]=(~U[0]&~U[1]&U[2]&~U[3]);
	assign HEX0[3]=(~U[0]&~U[1]&~U[2]&U[3])|(~U[0]&U[1]&~U[2]&~U[3])|(~U[0]&U[1]&U[2]&U[3]);
	assign HEX0[4]=(~U[0]&~U[1]&~U[2]&U[3])|(~U[0]&~U[1]&U[2]&U[3])|(~U[0]&U[1]&~U[2]&~U[3])|(~U[0]&U[1]&~U[2]&U[3])|(~U[0]&U[1]&U[2]&U[3])|(U[0]&~U[1]&~U[2]&U[3]);
	assign HEX0[5]=(~U[0]&~U[1]&~U[2]&U[3])|(~U[0]&~U[1]&U[2]&~U[3])|(~U[0]&~U[1]&U[2]&U[3])|(~U[0]&U[1]&U[2]&U[3]);
	assign HEX0[6]=(~U[0]&~U[1]&~U[2]&U[3])|(~U[0]&U[1]&U[2]&U[3])|(~U[0]&~U[1]&~U[2]&~U[3]);

endmodule
 

Mikebits

Well-Known Member
I am not familiar with Verilog, as I have only used VHDL, but have you created a sim file? If not, then I suggest you do so as this is a good debugging tool.
 

BrownOut

Banned
To assign values to flip-flops, just use an always block with clock edge signal, and reset edge, in the sensitivity list. Make sure flip-flop signals are defined as registers. Use non-blocking assignments:

ie

...
...
reg My_flip_flop;
wire clock, reset, sig_to_capture;

always @(posedge clock or posedge reset)
begin
if (reset) My_flip_flop <= 0;
else if (clock)
My_flip_flop <= sig_to_capture;
end
end

...

Excuse any syntex issues. Been out of work for 3 months now.
 
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