SPST Xilinx FPGA Debouncing

Hello all,

I am trying to create a switch debouncer for the Xilinx Spartan 6 FPGA. I am using a push button switch as a clock for a rising edge T flip flop. (Down counter). I am creating it from the schematic and when I use a switch as an input it only gives me one line to work with. If it were a SPDT switch, I would use SR latch debouncing but I have to make one from basically a SPST switch. I don't know VHDL so my next guess was to just use a counter and change the position for a longer/shorter delay. Is there any other way to debounce a SPST switch digitally? (No analog components, only gates unfortunately, due to my lack of VHDL knowledge).

You would need to add a delay after the first bounce which inhibits the circuit from responding again, so it ignores all bounces after the first switch contact. The delay should probably be on the order of 100ms.