Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

SPI Modes

Status
Not open for further replies.
Hi Ian,
Thank you.

I thought that "sent / propogated" means putting the bit on the SDO line.

But, according to what you say, the data bit firstly appears on the SDO line and only then it is sampled and transmitted.

What does it mean if so to transmit the data?
 
All we need worry about is the buffer.... We place the data in a buffer... The module can sample the buffer's MSbit then transmit it... Whilst the new data is shifted in at the LSbit... We choose the mode to suit the external hardware...
 
Thank you Ian.

So how do you explain that in CPHA=CPOL=1, we firstly transmit the data (falling edge) and only then sample the data (rising edge)?
 
hi RF,
This is a clip showing the 'shift' and 'strobe' for SPI.
E
 

Attachments

  • AAesp06.gif
    AAesp06.gif
    9.7 KB · Views: 147
Thank you Ian.

So how do you explain that in CPHA=CPOL=1, we firstly transmit the data (falling edge) and only then sample the data (rising edge)?

The sampling of the data isn't in our control!!! The SPI module just sends..... The reception is another thing.

When we want to get a byte from an external device we send a byte to it so we can get a byte back...

The SD0 line doesn't need to be bothered with...

Are you making a software SPI routine? I can't think why you need to worry about the transmitting / receiving part..
 
Ian,
I deeply thank you for your support.

I'm trying to understand how SPI works, and not just how to code it, which is more simpler.

I read in Wiki that:
Wikipedia said:
Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle. For all CPOL and CPHA modes, the initial clock value must be stable before the chip select line goes active.

That makes a lot of sense - I think I got that part :)

Thank you Ian for your awesome support :)


Could you please explain what is that trailing bit circled with GREEN?

SPI_CPHA0_CPOL0.jpg
 
Status
Not open for further replies.

Latest threads

Back
Top