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SPI Modes

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electroRF

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Hi,
I'm wondering about the following timing diagram from Wikipedia (SPI term), regarding SPI Mode 0,0:

in SPI Mode 0,0, the data is transmitted at falling edge.

Therefore, how come in the diagram, the first falling edge (in CPOL = 0) occurs just before bit #2 is transmitted? (in CPHA = 0)

I expected the first falling edge to occur just before bit #1 is transmitted.

How come the 1st bit was transmitted before the first falling edge?

thank you.
SPI_timing_diagram2.svg
 
Last edited:
hi RF,
Look at page 25 of this pdf.
E
 

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Hi Eric,
Thank you for your comment.

I actually already have this Microchip PDF.

Page 25 does not add any info.

Also, the only timing diagram in this PDF is for SPI MODE 1,1, which is at page 9.
 
hi,
This pdf is also from microchip [ page 23-11]
E
 

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Thank you Eric.

I have a specific question on the timing diagram from the this great tutorial.

In CKE = 0 mode, bit#0 on the SDO line has much longer duration, than in CKE = 1 mode.
Why is that?

timing.jpg
 
hi RF,
All that the d/s waveform is showing is that the SD0 line remains in the state of the last bit 0 transferred.
Note also that at the Start [ the greyed SD0] is shown as being indeterminate, whatever the last state was.

E
 
Hi Eric,

So why doesnt the SDO line remain in the state of the last bit 0 transferred, when CKE = 1?

I think there's a special meaning for that.
 
Hi Eric,

So why doesnt the SDO line remain in the state of the last bit 0 transferred, when CKE = 1?

I think there's a special meaning for that.

My reading of spec and timing diagrams on what's happening:
Starting from the first sent bit of the buffer, the last SCK edge (CKE = 1) means the final bit of 8 has already been sent out from the SSPSR shift-register/buffer to the pin and the final slave bit of 8 should already be in it from the input pin , if it latches new data in and out at that point then the first to send bit from the next 8 bits of data could be on the output pin.

Most sdcards work with mode 0,0 (CKP =0, CKE =1)

bit 8 CKE: SPIx Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)

bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
 
Hi Nasapook,
Thank you!

I was referring to the mode - CPHA = 0, CPOL = 0.

At that mode, the bit#0 extends much longer after the last edge - why?

Moreover, at that mode, bit #0 is sampled with no Rising Edge present - how is that?
 
Last edited:
hi RF,
Did you read pages 26 thru 29 of the last SPI datasheet I posted.?
E
 
Hi Nasapook,
Thank you!

I was referring to the mode - CPHA = 0, CPOL = 0.

At that mode, the bit#0 extends much longer after the last edge - why?

Moreover, at that mode, bit #0 is sampled with no Rising Edge present - how is that?

'CKP =0, CKE =1' is 'CPOL = 0, CPHA = 0'.
MCHP bits -> original Moto bits.

C18 header define
#define MODE_00 0b00000000 // Setting for SPI bus Mode 0,0
//CKE 0x40 // SSPSTAT register
//CKP 0x00 // SSPCON1 register

**broken link removed**
Section 4.4
 
Last edited:
Hi NSA,
Thanks a lot for the PDF!

I have a question on its timing diagram from CPHA = 0, CPOL = 0

In this mode, the bytes are propogated on the SDO line on the falling edge.

However, as you can see in the diagram - the 1st byte (circled in red) is propogated on the SDO line before the falling edge (circled in red).

How do you explain it please?

SPI_CPHA0_CPOL0.jpg
 
Hi Ian,

Could you explain how come I mis-read it?

I see the same phenomena in your Graph for CPHA = CPOL = 0.

The first byte appears on the SDO line BEFORE the first falling edge of the clock - how come?
 
I see the same phenomena in your Graph for CPHA = CPOL = 0.

You are looking at four actual modes

leading edge!!!
CPHA = 0 CPOL = 0 ( top diagram... Rising edge of clock )
CPHA = 0 CPOL = 1 ( top diagram... Falling edge of clock )
Trailing edge!!
CPHA = 1 CPOL = 0 ( Bottom diagram... Falling edge of clock )
CPHA = 1 CPOL = 1 ( Bottom diagram... Rising edge of clock )

If you look carefully if you shift the diagram the read is in the same place on all four...
 
Hi Ian.
thank you again.

I think you did not regard my question.

In CPHA=CPOL=0, the data should be propogared to the SDO line at falling edge, right?

so, how come before the first falling edge, the first byte was already propogated to the sdo line?
 
It isn't.....
CPHA = 0, CPOL = 0.. is the leading edge rising...
CPHA = 0, CPOL =1.. is the leading edge falling...

CPHA = 0, CPOL = 0.. CANNOT be falling edge...

You are marking CHPA = 1.. Trailing edge...
 
Hi Ian,
The red Circles I marked are from CHPA = 0 Graph.

CPHA = 0, CPOL = 0.. CANNOT be falling edge..

According to Protocol, in CPHA=CPOL=0, the data is propogated in falling edge - do you disagree with that?
 
Hi Ian,
The red Circles I marked are from CHPA = 0 Graph.
Read the wiki explanation....
CHPA = CPLO = 0..
The data is read on the rising edge and propagated on the falling edge... Propagated means written / transmitted..

You do know that SPI is a circular buffer? As far as we are concerned, we really only need to know when the buffer is read...
 
I have re-read the entire thread.... I see what you need to know.... I thought your confusion was the SPI module reading the buffer.... As the last post ( hopefully explains ), the SD0 is sampled first, then sent/propagated... You don't need to know about the propagation... It's internal....

Sorry about the confusion...
 
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