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# [Solved] Need help regarding for modify decade counter waveform

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#### Green7

##### New Member
I'm new to this forum, sorry my english is not that good, just use a translator, and my knowledge about circuits and electronics is very low,
Here I want to ask for help from fellow forumers

For example clock input from ic555 t-on 30% and t-off 70%. see the example in the picture

If using ic4017 decade counter and activate 3 outputs, ouput from ic4017 such as A1, A2, A3

What is the easiest way to get outputs like B1, B2, B3, which only follows the T-on clock input

Hope fellow forumers can help me

[Update Solved 27 Mar 2023 ]

I update for reference, After searching for AND gates using transistors,

By using an NPN transistor as an AND gate, the voltage and Ampere ouput B1, B2, B3 can be controlled higher and wider depending on the input value or Vcc

And if the output value from ic4017 is enough, we can use only 1 NPN transistor to get the output B1, B2, B3,

Credit to Diver300

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The easiest way is to have an AND gate for each output.
One input to each AND gate would be the clock input.
The other input to the AND gate would be one of A1, A2 or A3.
The output of the AND gate would have the waveform that you want.

You diagram does NOT look like the output of a decade counter.
That is because the CD4017 is a 5-stage Johnson Counter with decoded outputs.
This is what you might get with AND gates. Too bad about the possible trailing edge glitches.

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To Papabravos point here is the timing diagram :

Regards, Dana.

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The easiest way is to have an AND gate for each output.
One input to each AND gate would be the clock input.
The other input to the AND gate would be one of A1, A2 or A3.
The output of the AND gate would have the waveform that you want.
Thank you very much Diver300, You mean like the diagram below

In theory, I think it would work well.

I think my problem is solved, Diver300, thanks again.

You diagram does NOT look like the output of a decade counter.
That is because the CD4017 it is a 5-stage Johnson Counter with decoded outputs.
This is what you might get with AND gates. Too bad about the possible trailing edge glitches.
View attachment 140953

Papabravo, I don't know the difference between 5 Stage Johnson Counter, my knowledge about electronics is very low

If refer to the video about 5 Stage Johnson Counter Using 4017BP

Output ic4017BP as diagram danadak gives

I think the guide provided by Diver300 can work well

Anyway, thank you Papabravo and danadak for the feedback given

There is no time like the present to learn what is under the hood.

Thank you very much Diver300, You mean like the diagram below

View attachment 140954

In theory, I think it would work well.

I think my problem is solved, Diver300, thanks again.
Yes, that is what I meant.

If you also connect the Q3 output of the 4017 to the reset input of the 4017, you will get the waveform that you showed in your first post.

There is no time like the present to learn what is under the hood.
You are right, the 5 Stage Johnson Counter output is different from the normal decade counter.

Thank you for the explanation link provided

Yes, that is what I meant.

If you also connect the Q3 output of the 4017 to the reset input of the 4017, you will get the waveform that you showed in your first post.
Q3
previously I thought Q4 needed to be connected to the reset to activate the 3 outputs Q0, Q1 and Q2

Thank you

Q3
previously I thought Q4 needed to be connected to the reset to activate the 3 outputs Q0, Q1 and Q2

Thank you
It's Q3.
Starting at Q0 is on.
Next rising edge of clock causes Q1 to turn on
Next rising edge of clock causes Q2 to turn on
Next rising edge of clock causes Q3 to turn on. If that is connected to the reset, very soon after than, Q3 will turn off and Q0 will turn on, and it's back to the start.

Q3
previously I thought Q4 needed to be connected to the reset to activate the 3 outputs Q0, Q1 and Q2

Thank you
It's Q3.
Starting at Q0 is on.
Next rising edge of clock causes Q1 to turn on
Next rising edge of clock causes Q2 to turn on
Next rising edge of clock causes Q3 to turn on. If that is connected to the reset, very soon after than, Q3 will turn off and Q0 will turn on, and it's back to the start.
Sorry, I misunderstood, when you write Q3 you mean no. 4, when I write Q4 I also mean no. 4, hehehe

excuse my stupid mistake

I update for reference, After searching for AND gates using transistors,

By using an NPN transistor as an AND gate, the voltage and Ampere ouput B1, B2, B3 can be controlled higher and wider depending on the input value or Vcc

And if the output value from ic4017 is enough, we can use only 1 NPN transistor to get the output B1, B2, B3,

Credit to Diver300

You should not have resistors between the bases of the transistors and ground. You want the base voltage to be near the supply when the clock is on. The output will be around 0.6 V below the base voltage when the output is on.

You will need some load on the output for the transistors to work.

The base current will be limited by the base resistors, and when there is no voltage on the collector, that base current will still be available on the outputs, so you need to make sure that the base resistors alone will not turn on whatever load you intend to connect.

I fear you will still get the glitch as pointed out by papabravo.

Mike.

It has been a while since somebody seriously suggested doing logic with resistors and discrete transistors. RTL was abandoned quickly for reasons which were manifestly obvious to practitioners of that era.

You should not have resistors between the bases of the transistors and ground. You want the base voltage to be near the supply when the clock is on. The output will be around 0.6 V below the base voltage when the output is on.

You will need some load on the output for the transistors to work.

The base current will be limited by the base resistors, and when there is no voltage on the collector, that base current will still be available on the outputs, so you need to make sure that the base resistors alone will not turn on whatever load you intend to connect.
I will try if it is not necessary resistor to base transistor to ground

in my estimation, the transistor base resistor to the ground is just to ensure that the transistor is completely closed, because some transistors are not completely closed if they are not supplied with a little negative (-) on the base, usually the resistor I use is above 10k depending on the transistor.
due to the output from ic4017 for example for the first wave/clock, Q0 remains On even though the clock input is in t-off condition.

I'm very naive about electronics, I'll quote what you said, I'll try and error from the basics you gave.

Thanks for the information provided

Transistors are operated by current not voltage, you're probably getting confused with FETs.

Mike.

I fear you will still get the glitch as pointed out by papabravo.

Mike.
It has been a while since somebody seriously suggested doing logic with resistors and discrete transistors. RTL was abandoned quickly for reasons which were manifestly obvious to practitioners of that era.
My electronics knowledge is very poor, I couldn't achieve part of what you said

I will try and error, hope there is no problem and succeed in doing it with the basic knowledge I have

Transistors are operated by current not voltage, you're probably getting confused with FETs.

Mike.
Thanks for the information given, My electronics knowledge is very poor, I need to learn more about electronics

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