Simple timing issue inside Beta CPU

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zhaniko93

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Hello all.
I currently watching mit ocw 6.004 course and have this question: here is part of CPU.
Everything is combinational here, except Write operation of Register File. I also attach timing diagram for Register File. As far as I understand, this won't work, will it? How to accomodate setup and hold times, so that write will require only one cycle?
 
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