Hello,
The simplest way to build a divide by N counter is to first build a binary count circuit (FF's) that can count up to at least N and then build a detector circuit that can detect a count of N and have the output of that detector circuit reset all the FF's to zero.
For example, for a divide by 6 circuit we would need at least 3 Flip Flops and a little circuit that can detect a binary 6 (because N=6). The detect circuit is then used to reset all the FF's to zero. For this example, the count would go 0,1,2,3,4,5, and as soon as the count becomes 6 the detect circuit resets all the FF's back to zero so the count again goes 0,1,2,3,4,5. So it will keep repeating, 0,1,2,3,4,5, 0,1,2,3,4,5, 0,1,2,3,4,5, etc., which is a divide by six counter.
The detect circuit is often nothing more than a NAND gate with enough inputs to detect the full bit width of the counter plus some inverters. For the example above, we would be using 3 bits thus we would need at least a 3 bit NAND gate. A binary 6 with three bits is 110 so we need to invert the zero bit and run that into one NAND gate input and run the other two right into the NAND gate. Thus, the NAND gate outputs a 1 until such time as the count becomes equal to 6 and then the NAND outputs a 0 which resets all of the FF's (many FF's have an inverted true reset input ie 'Not Reset').
There is a trick we can use however, because the above detect circuit assumes a totally random count but the count from a binary counter is not random but is in sequence 0,1,2,3,..., etc. This means that some states can only appear after some other states and that means some other states will never appear. This means we can simplify the detect circuit. If we assume that the counter starts at zero the count goes 0,1,2,3,4,5, and so far all that time the 1st and 2nd bits never both equaled 1 at the same time, but at a count of 6 suddenly they both do, so we can simplify the detect circuit knowing this and get away with using only a single two input NAND gate with the inputs connected to bits 1 and 2 (not to bits 0 and 1). In this way, when a count of 110 occurs the NAND output goes to 0 and resets all the FF's but never any other time will this occur.
Thus, with a 3 bit counter and a single two input NAND gate we have constructed a divide by 6 counter.
Other counters are constructed in a similar way sometimes needing a NAND gate with many more inputs, but it never hurts to look for short cuts either.