Both of your assertions are true (at least if I interpret your wording correctly). The first timing diagram is valid, the second one is either incomplete or poorly represented.
If the register file is a clocked device (as the timing diagram indicates), then you are correct that the WA and WD inputs need to meet the setup and hold times.
But the output of the register file will propagate through various logic to (potentially) become new values for WA and WD. So there is some validity to the second timing diagram. The over all propagation delay is the register file clock to output, and any other asynchronous delays from the other logic. But the second timing diagram shows the WA and WD signals going from a valid state to an invalid state prior to the next rising edge of the clock. This is either incorrect, or incomplete. There could be other signals that would explain why WA and WD are no longer defined, but they are not shown. IF the only variables are the outputs of the clocked register file, then the 2nd diagram is wrong and WA and WD would remain valid until the next rising clock edge.
Blah, blah, blah disclaimer on not knowing the exact parts in question and not knowing if they are dual clock edged devices, and not knowing if there are unknown analog or high frequency reflection issues involved in the signals., etc.
-Jim