Setup and Hold times

[zhaniko93]

Consider a simple CPU View attachment 68630. Here, REGFILE write is sequential, so it has to accomodate Setup and Hold time requirements: data on WD and WE(write enable) has to be valid TSetup time before valid clock transition, but only after clock transition, propagation delays of Instruction memory, Control logic and some other things, become WD and WE valid. that is, not TSetup before clock transition, but even propagation times after clock transition become they valid, which violates setup and hold time constraints, so it shouldn't work, but it works! how?

 

[unclejed613]

a timing diagram might be helpful.

 

[zhaniko93]

View attachment 68632 Sorry for bad quality

 

[JimW]

Both of your assertions are true (at least if I interpret your wording correctly). The first timing diagram is valid, the second one is either incomplete or poorly represented.

If the register file is a clocked device (as the timing diagram indicates), then you are correct that the WA and WD inputs need to meet the setup and hold times.

But the output of the register file will propagate through various logic to (potentially) become new values for WA and WD. So there is some validity to the second timing diagram. The over all propagation delay is the register file clock to output, and any other asynchronous delays from the other logic. But the second timing diagram shows the WA and WD signals going from a valid state to an invalid state prior to the next rising edge of the clock. This is either incorrect, or incomplete. There could be other signals that would explain why WA and WD are no longer defined, but they are not shown. IF the only variables are the outputs of the clocked register file, then the 2nd diagram is wrong and WA and WD would remain valid until the next rising clock edge.

Blah, blah, blah disclaimer on not knowing the exact parts in question and not knowing if they are dual clock edged devices, and not knowing if there are unknown analog or high frequency reflection issues involved in the signals., etc.

-Jim

 

[zhaniko93]

Thanks for your reply, Jim!
I got the point. I made a new timing diagram, which better represents the problem, so please take a look: View attachment 68675 Here, we know that T0>Tcd and T0<Tpd, but in order not to violate setup and hold times, T0 must be bigger than T(hold), so we have to somehow increase contamination delay, I think? I got it how not to violate setup time: just decreace clock frequency, but what about the hold time? thanks for trying to help!