zhaniko93
New Member
Consider a simple CPU View attachment 68630. Here, REGFILE write is sequential, so it has to accomodate Setup and Hold time requirements: data on WD and WE(write enable) has to be valid TSetup time before valid clock transition, but only after clock transition, propagation delays of Instruction memory, Control logic and some other things, become WD and WE valid. that is, not TSetup before clock transition, but even propagation times after clock transition become they valid, which violates setup and hold time constraints, so it shouldn't work, but it works! how?
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