second order sigma delta modulator

hi,
i want to design second order sigma delta modulator in 0.35u cmos tech.
i want to have good material on the analog design on the two integrators in specific. i have read about them..but a few topics are still vague.

it would be helpful if i can get the links on the analog cmos design of the two integrators and the constraints in designing them to maintain stability when they are cascaded.

Thanks

--b'b