I am having a problem in LTSpice with a basic SCR circuit that I can't seem to work out, just wondering if someone could have a look for me & see what I am overlooking?
As you will see in the attachments I have two SCR's, one is triggered for the power flow of the positive half cycle & the other one for the power flow of the negative half cycle.
Attachment: SCR TEST, shows this to be working ok.
In the second attachment SCR TEST 2, I have delayed the trigger firing by 5ms on both SCR's, this is where I am getting a problem, the positive half cycle shows the delay but the negative half cycle does not?
Not sure what I am doing wrong?
Cheers
As you will see in the attachments I have two SCR's, one is triggered for the power flow of the positive half cycle & the other one for the power flow of the negative half cycle.
Attachment: SCR TEST, shows this to be working ok.
In the second attachment SCR TEST 2, I have delayed the trigger firing by 5ms on both SCR's, this is where I am getting a problem, the positive half cycle shows the delay but the negative half cycle does not?
Not sure what I am doing wrong?
Cheers