SCR Test

[willeng]

I am having a problem in LTSpice with a basic SCR circuit that I can't seem to work out, just wondering if someone could have a look for me & see what I am overlooking?

As you will see in the attachments I have two SCR's, one is triggered for the power flow of the positive half cycle & the other one for the power flow of the negative half cycle.

Attachment: SCR TEST, shows this to be working ok.

In the second attachment SCR TEST 2, I have delayed the trigger firing by 5ms on both SCR's, this is where I am getting a problem, the positive half cycle shows the delay but the negative half cycle does not?

Not sure what I am doing wrong?

Cheers

 

[Timescope]

The gate trigger sources should be connected between gate and cathode, not to ground. You would need to use a pulse transformer or opto-coupler to trigger the thyristors with a ground referenced signal.

Timescope

 

[KeepItSimpleStupid]

My SCR knowledge is not up to snuff, but try flipping the polarity of v2 or V3 on the errant pulse.

 

[MikeMl]

The gate trigger pulse for any SCR must be applied to the gate with respect to the cathode. Your connections make no sense. You are trying to trigger them with respect to a ground which is the whole supply voltage removed from the cathode voltage.

 

[willeng]

Thanks for the replies,
Ok, I've got it now.

Thanks Again