The circuit you show is not really suitable for building with discrete components, or for voltage level translation.
Both FETs will be turned on briefly during each input transition, and with the input only reaching 3.3V the upper FET may be permanently conducting to some extent.
The upper FET will also be receiving a rather higher gate-source voltage when on, which could explain the overshoot?
Some of the pulse on the scope could also be capacitive feedthrough internally to the FETs, plus the dive asymmetry?
(I don't think it's a scope artefact, as they are usually symmetrical & there is no negative overshoot at all).