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# Pulse speed reducer???

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#### Wildfox

##### New Member
Any one know a simple way to build a pulse speed reducer, I need to reduce the input pulses by 20%.

i.e. for every 5 pulses in, I want 4 going out.

Any help would be great,
Thanks

Drew

Hi Wildfox,,

Would something like this help?

Use a 7490 to divide by five, then two simple doubler circuits from a single 74386 ic. 2 x 2 / 5 = 4/5. Divide by five circuit below-

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• Frequency_divider_with_7490.gif
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thanks

Thanks guys, I think I know what direction to go in now.
You've been a big help!

I think, You can use this circuit....

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• 5_1puls.jpg
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Nice design, Sebi. The output will have an asymmetrical output, due to the two missing pulses. Wildfox, in case your application must maintain duty cycle symmetry, I fleshed out the design I mentioned earlier.

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• pulse_reducer.gif
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Hi Sebi,
That is almost exactly what I was thinking of. My schematic writing software is so much trouble though.
Your schematic is perfect, what do you use?

Seeker,

i just use the Paint for modification (with copy/paste) of sematics. I have many sematics on HDD, and when somebody need a circuit, i can draw it.(just 5...15min)

Sebi, your circuit will probably put out an unwanted glitch after each group of 4 pulses. Draw a timing diagram which includes propagation delays. I think you can fix it by putting an inverter in the clock line which goes to the counter.
Mogur, I don't know what you're smoking. There's no way that is going to put out a symmetrical duty cycle. First, the 7490 does not have a symmetrical duty cycle. Second, your circuit attempts to create two pulses for every transition of the 7490's output, and if it did, each pulse would have a width equal to the propagation delay of a 74386 gate (about 30 nanoseconds). In fact, for each transition of the 7490's output, you will only get one pulse whose width is equal to twice the propagation delay of a 74386 gate. Again, do a timing diagram.
The only way I know of to get symmetry over a range of frequencies is with a phaselocked loop (PLL), where the VCO (Fout) is running at 4/5 of the input frequency (Fin). You have to divide Fin by 5, divide Fout by 4, and run these two signals to the phase detector of the PLL.

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