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dramrattan

Member

• Apr 20, 2009

• #1

A program with 6 assembly instructions has to be executed on an 8 bit pipelined CPU. The CPU has a 6 bytes instruction pre-fetch Queue, which fetches the instructions and fills the pipeline
1] What would happen if the 5th instruction in the program is an unconditional jump / branch ?
2] Can the number of address lines for the CPUs be determined?

 

Sceadwian

Banned

• Apr 20, 2009

• #2

Again, not enough information to answer your question, how many instructions does it take to execute the unconditional jump or branch and how long it takes to re-fill the pipline. If you want us to do your homework for you the least you should do is provide enough information to answer it.

 

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dramrattan

Member

• Apr 20, 2009

• #3

Sorry i just use it to verify my answers...Won't do it anymore...seems to get everyone on the wrong side.

 

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dramrattan

Member

• Apr 21, 2009

• #4

Considering the PIC16F877:

All i understand is that an unconditional jump/branch takes two instructions instead of one. From reading up about prefetching with pipelining in microprocessors it causes stalling of the processor when a condition like this occur. Not to sure about determining the number of address lines.

 

Last edited: Apr 21, 2009

Sceadwian

Banned

• Apr 21, 2009

• #5

It stalls until the instruction pipeline is filled, so however deep the pipeline is. I thought it was worked into the cycle count on the branch instructions.

 

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dramrattan

Member

• Apr 21, 2009

• #6

Thanks i read something like what you mentioned but wasn't sure about what it was trying to explain but nevertheless i think i got the basic point about it.