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problem with lvs using cadence calibre tool

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salar_1991

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hi i'm testing the layout for my circuit using cadence calibre tool that is a transimpedance amplifier and im using cadence 6.14. drc test is ok but i encountered some errors in lvs check . there is 16 errors including 1 port error which points to gnd and i couldn't fix it and i checked the layer of pin and lable problem is not from that . there are 4 incorrect instance errors that's pointing to 4 spiral inductor in the circuit and there are 11 net errors. can anyone help me ? thanks in advance .
 

Beau Schwabe

Active Member
I am a 15 year IC layout veteran using Virtuoso , but without being able to visualize your actual layout and schematic it's hard to say what might be an issue.

Many times inputs can get confused in the LVS tools creating false errors down the line that can usually be fixed with liberal node labeling in both the schematic and layout, but I doubt that is causing your issue. If the inductor is not defined properly with two nodes, then that can cause a net naming issue.... The "FIX" solution there is to use a dummy resistor which is simply a piece of metal defined with two nodes in the SAME metal layer as your inductor is in or to define your inductor properly.
 

Beau Schwabe

Active Member
Your gnd error is most likely from the substrate connection in the right nmos transistor. The left nmos is connected to gnd properly, but the right one is going through the inductor. That can cause all kinds of problems by injecting noise into the substrate causing latchup. The pmos transistors are probably giving related errors, but can probably be fixed if you tie the NWELL properly. IOW both pmos transistors must be in a separate NWELL and spacing rules apply because the NWELL's are considered at different potentials. It's hard to tell in the layout the detail of the transistor structures. The inductors look ok as far as their A&B terminal but as far as their ground terminal, you might have a similar problem with them as the transistors. Depending on the inductor model used, they may need to sit in their own NWELL and have the NWELL properly tied to GND or VDD. One last thing ... I don't see any guard rings in your design. To prevent the guard rings from coupling into your coil as a parasitic secondary coil you can create a "notch" where the guard ring does not complete a circuit. Without guard rings, you can have mutual parasitic inductance between your coils. Guard rings can help minimize this. Another way to minimize mutual parasitic inductance is to design your inductors as a serpentine or interdigitated style.
 

Beau Schwabe

Active Member
when i connect the bulk of nmoses directly to ground and bulk of pmos directly to vdd it ruins the result
....Not quite .... The NMOS PWELL needs to be at the same voltage potential as the substrate always, you can't avoid this unless you are using a special process that allows for hot PWELL.... for the PMOS, the NWELL is already isolated, you just need to make sure it is at the same potential as the Source connection of the transistor sitting inside of the nwell. because both nwells are at a different potential, there are DRC spacing rules that need to be considered between the two nwells
 
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