Hi,
I am not sure if this is strictly the correct forum for this query but here goes.
I am currently interfacing a PowerPC 440 GX to an FPGA via the PowerPC´s external bus controller (EBC).
In the PowerPC handbook, timing diagrams are given which show how a transfer takes place. The interface consists of a clock, address, data and various control lines, which are all driven by the PowerPC on the rising edge of the clock that it sends.
The problem that I am having is that on the timing diagrams it does not show the exact delay between for example the rising edge of the clock and the assertion of the address bits. I want to constrain the interface in the FPGA and want to know how long it will take before the address outputs (for example) have reached the respective value and can be read correctly.
I am thinking that the rising edge of the clock and the assertion of the address bits will not occur exactly at the same time. I would like to obtain a specification for this time gap (which I am unable to find in the handbook or anywhere else) and then add this to the board delays to succesfully constrain the interface in the FPGA.
Does anybody have any ideas on this, or know where I could obtain these figures? I have attached the Power PC 440 GX handbook. (sorry for the size). On page 992 a timing diagram shows where the clock edge rises and the address bits are driven but a min or max time gap between the assertion of the clock and the address bits is not given.
I really appreciate any ideas on this.
Many thanks for your time.
I am not sure if this is strictly the correct forum for this query but here goes.
I am currently interfacing a PowerPC 440 GX to an FPGA via the PowerPC´s external bus controller (EBC).
In the PowerPC handbook, timing diagrams are given which show how a transfer takes place. The interface consists of a clock, address, data and various control lines, which are all driven by the PowerPC on the rising edge of the clock that it sends.
The problem that I am having is that on the timing diagrams it does not show the exact delay between for example the rising edge of the clock and the assertion of the address bits. I want to constrain the interface in the FPGA and want to know how long it will take before the address outputs (for example) have reached the respective value and can be read correctly.
I am thinking that the rising edge of the clock and the assertion of the address bits will not occur exactly at the same time. I would like to obtain a specification for this time gap (which I am unable to find in the handbook or anywhere else) and then add this to the board delays to succesfully constrain the interface in the FPGA.
Does anybody have any ideas on this, or know where I could obtain these figures? I have attached the Power PC 440 GX handbook. (sorry for the size). On page 992 a timing diagram shows where the clock edge rises and the address bits are driven but a min or max time gap between the assertion of the clock and the address bits is not given.
I really appreciate any ideas on this.
Many thanks for your time.
