I don't follow how the output frequency becomes N*f_in when the phase detector is fed with the reference frequency f_in and feedback N*f_in. I understand that the output of the phase detector is a voltage proportional to the phase difference between the two inputs. The low pass filter attenuates high frequency content. I don't understand how the output of the VCO is at a frequency that is N times the input supplied to the frequency reference input.
You have an oscillator running at some frequency, lets say 100MHz.
100MHz free running oscillators can drift due to temperature, voltage changes etc.
We want to stabilise the oscillator.
We have a good crystal oscillator which runs at 500kHz.
So lets make a phase locked loop.
We make the 100MHz oscillator so that it can be tuned by a voltage signal.
We make a digital divider, which divides the 100MHz by 200. We not have 500kHz.
We use a phase comparator to compare the divided 500kHz with the accurate standard 500kHz.
The output of the phase comparator and low pass filter is a DC signal which can tune the 100MHz oscillator.
We arrange the circuit so that if the 100MHz is low in frequency, the output of the phase detector/LPF/amplifier will tune the 100MHz oscillator up in frequency so that it is exactly 100MHz.
And similarly if the 100MHz is high in frequency, the output of the phase detector/LPF/amplifier will tune the 100MHz oscillator down in frequency so that it is exactly 100MHz.
Thanks a lot, everyone!
Now I'm really confused about the function of phase comparator. I had thought that the output of the phase detector is a voltage proportional to the phase difference between the two inputs but from your reply it seems more like if the output of the phase detector is a voltage proportional to the frequency difference between the two inputs. Could you please comment on that?
If there is a frequency difference, the phase difference will not be constant, and will get larger and larger over time. As the phase difference gets larger, the signal to the VCO gets larger, so the frequency gets larger which reduces the frequency difference, so the phase changes more slowly, until eventually there is a constant phase difference and no frequency difference.
Now I'm really confused about the function of phase comparator. I had thought that the output of the phase detector is a voltage proportional to the phase difference between the two inputs but from your reply it seems more like if the output of the phase detector is a voltage proportional to the frequency difference between the two inputs. Could you please comment on that?
In practice that is what happens.Now I'm really confused about the function of phase comparator. I had thought that the output of the phase detector is a voltage proportional to the phase difference between the two inputs but from your reply it seems more like if the output of the phase detector is a voltage proportional to the frequency difference between the two inputs. Could you please comment on that?
Agreed.In common with many posts on here, you're over thinking it
Hi,
Could you please help me with the queries below? I understand that you might find it frustrating that I'm asking questions about the same topic but I'm only struggling to get a proper understanding of it. Thank you!
Please have a look on the attachment.
Question 1:
I don't really understand where it says, "The two frequencies cause the phase difference to be a beat behaviour". What does it mean? Is it suggesting that two different frequencies cause beat behavior where 'beat' might suggest oscillation.
Question 2:
It says, "The average output is zero if ω1≠ω2". What does it mean? Is it saying that average output of phase detector is zero? If the average output of phase detector is really zero then VCO would keep on oscillating with its free-running frequency which is not possible in case of ω1≠ω2.
Q2. If the two frequencies continue to differ, so ω1≠ω2, then the output of the phase detector will continually vary from maximum (at 0 degrees phase difference) to minimum (at 180 degrees phase difference). If the phase detector has a maximum that is positive and a minimum that is negative by the same amount, then the average output will be zero.
It's a phase detector, so the output is proportional to the phase difference.
It depends on the particular phase comparator. In most PLLs it doesn't matter which way round the phase comparator works. One way round will end up with the phase of the VCO being in advance of the reference signal, the other will end up with the VCO lagging the reference signal. The frequencies will end up the same either way. I hadn't worried about the direction of operation in my post.Thank you so much! Your reply is really helpful.
Wouldn't it be maximum when the input frequencies are 180 degrees out of phase and minimum when they are in phase?
Thank you so much! Your reply is really helpful.
I don't understand how expression 3.49 shown below is reached in this text from my previous post. Could you please have a look at it?
I tried it but couldn't proceed any further.
Thank you very much!
Question 1:
It looks like, at least according to some of the references I have been through, when a PLL is locked the input/reference frequency and output frequency which is coming out of VCO are the same but the phase difference between them would be 90 degrees. In other words, when the phase difference is 90 degrees, it is said that the phase difference is zero.
"The goal is to generate a VCO output whose frequency is the same as the frequency of the received signal and phase is different from the phase of the received signal by 90 degrees."
[Introduction to Digital Communications, Ali Grami, 2016 edition, PDF page #369]
By the way, is there any reason that why the 'inherent' phase difference is 90 degrees and not simply 0 degrees? One reason might be that it's more easier to implement with 90 degrees phase difference rather than going 0 degrees.
Let's assume that the phase detector has a maximum output at 180 and a minimum output at 0.Question 2:
The following text is taken from this attachment. The difference between the two definitions is seemingly so subtle that the definition of Capture Range eludes the understanding.
Lock Range
The lock range of a PLL is the range of input frequencies over which the VCO can remain locked onto and track the input frequency. It is related to the maximum phase difference that can be detected. In our discussion, we are assuming that the phase detector can produce an output voltage for Δφ between -90° and +90°. At these limits, the phase detector produces a maximum output voltage, either negative or positive.
If the input frequency is too low or too high, the phase difference is outside the range of -90° and +90°. Therefore, the phase detector cannot produce the additional voltage needed for the VCO to remain locked on. At these limits, therefore, the PLL loses its lock on the input signal.
The lock range is usually specified as a percentage of the VCO frequency. For instance, if the VCO frequency is 10 kHz and the lock range is +/-20%, the PLL can remain locked on any input frequency between 8 and 12 kHz.
Capture Range
The capture range is different. Assume that the input frequency is outside the lock range. Then, the VCO is free running at 10 kHz. Now, assume that the input frequency changes toward the VCO frequency. At some point, the PLL will be able to lock onto the input frequency. The range of
input frequencies within which the PLL can reestablish the lock is called the capture range.
The capture range is specified as a percentage of the free running frequency. If f_0=10 kHz and the capture range is +/-5%, the PLL can lock on to an input frequency between 9.5 and 10.5 kHz. Typically, the capture range is less than the lock range because the capture range depends on the cutoff frequency of the low-pass filter. The lower the cutoff frequency, the smaller the capture range.
The cutoff frequency of the low-pass filter is kept low to prevent high-frequency components like noise or other unwanted signals from reaching the VCO. The lower the cutoff frequency of the filter, the cleaner the signal driving the VCO. Therefore, a designer has to trade off capture range against low-pass bandwidth to get a clean signal for the VCO.
Source: https://www.quora.com/What-is-lock-range-and-capture-range-of-phase-locked-loop-in-simple-terms
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