phase locked loop as a frequency multiplier

[PG1995]

Hi,

Could you please help me to understand the operation of a closed lock loop as a frequency multiplier?

Source #2 says, "Since the output of frequency divider is locked to input frequency fin, the VCO is actually running at a multiple of the input frequency. The desired amount of multiplication can be obtained by selecting a proper ÷N network.
∴Input to phase detector, fin=fo/N
∴fo=Nfin".

I don't follow how the output frequency becomes N*f_in when the phase detector is fed with the reference frequency f_in and feedback N*f_in. I understand that the output of the phase detector is a voltage proportional to the phase difference between the two inputs. The low pass filter attenuates high frequency content. I don't understand how the output of the VCO is at a frequency that is N times the input supplied to the frequency reference input.

Block diagram #1:

Source #1: https://electricalelctronic.blogspot.com/2012/02/phase-locked-loop-pll.html

Block diagram #2:

Source #2: https://www.electronics-tutorial.net/analog-integrated-circuits/phase-locked-loop/pll-applications/

Helpful links:
1: https://www.cardinalxtal.com/static/frontend/files/cardinal-phase-lock-loop-basics.pdf
2: https://www.sciencedirect.com/topics/engineering/phase-locked-loops

 

[Nigel Goodwin]

It's ever so simple - the phase detector compares the output from the div N counter with the reference, and creates an error voltage accordingly, this error voltage alters the VCO until the output of the div N counter equals the reference. It's a basic negative feedback loop.

By altering the division ration of the counter, you can alter the output frequency.

 

[JimB]

I don't follow how the output frequency becomes N*f_in when the phase detector is fed with the reference frequency f_in and feedback N*f_in. I understand that the output of the phase detector is a voltage proportional to the phase difference between the two inputs. The low pass filter attenuates high frequency content. I don't understand how the output of the VCO is at a frequency that is N times the input supplied to the frequency reference input.

Your problem may be that you are thinking in the "forward" direction through the block diagram ie Fin is converted to Fo.

Think of it more like this:

You have an oscillator running at some frequency, lets say 100MHz.
100MHz free running oscillators can drift due to temperature, voltage changes etc.
We want to stabilise the oscillator.
We have a good crystal oscillator which runs at 500kHz.
So lets make a phase locked loop.
We make the 100MHz oscillator so that it can be tuned by a voltage signal.
We make a digital divider, which divides the 100MHz by 200. We not have 500kHz.
We use a phase comparator to compare the divided 500kHz with the accurate standard 500kHz.
The output of the phase comparator and low pass filter is a DC signal which can tune the 100MHz oscillator.
We arrange the circuit so that if the 100MHz is low in frequency, the output of the phase detector/LPF/amplifier will tune the 100MHz oscillator up in frequency so that it is exactly 100MHz.
And similarly if the 100MHz is high in frequency, the output of the phase detector/LPF/amplifier will tune the 100MHz oscillator down in frequency so that it is exactly 100MHz.

Does that help?

JimB

 

[dr pepper]

The Vco goes into a divider, the output of the divider goes to the phase comparator.
The 2 freqs at the comparators input, ref freq and Vco freq are the same.
The phase comparator/loop filter generates a voltage that is comparable to the phase error (for type 2).
This voltage varies until the 2 phase comparator inputs are matched in phase.
Thats it, the comparator doesnt care what freq the Vco is, it just so happens in your case that the Vco is divided down, the chip still matches the freqs at the comparators input, it would still work if there was no divider.
Changing the division rate will change the Vco freq, the thing to take note is make sure the output freq is within range of the Vco's control.
Due to the way the complicated maths works (the function of the xor or whatever the phase comparator has) the ref frequency is multiplied by the Vco's divider ratio rather than divided.

 

[crutschow]

In summary, the PLL tries to adjust it's VCO frequency so the the input frequency and the divider frequency output are the same.
All the rest follows from that.

 

[PG1995]

Thanks a lot, everyone!

You have an oscillator running at some frequency, lets say 100MHz.
100MHz free running oscillators can drift due to temperature, voltage changes etc.
We want to stabilise the oscillator.
We have a good crystal oscillator which runs at 500kHz.
So lets make a phase locked loop.
We make the 100MHz oscillator so that it can be tuned by a voltage signal.
We make a digital divider, which divides the 100MHz by 200. We not have 500kHz.
We use a phase comparator to compare the divided 500kHz with the accurate standard 500kHz.
The output of the phase comparator and low pass filter is a DC signal which can tune the 100MHz oscillator.
We arrange the circuit so that if the 100MHz is low in frequency, the output of the phase detector/LPF/amplifier will tune the 100MHz oscillator up in frequency so that it is exactly 100MHz.
And similarly if the 100MHz is high in frequency, the output of the phase detector/LPF/amplifier will tune the 100MHz oscillator down in frequency so that it is exactly 100MHz.

Now I'm really confused about the function of phase comparator. I had thought that the output of the phase detector is a voltage proportional to the phase difference between the two inputs but from your reply it seems more like if the output of the phase detector is a voltage proportional to the frequency difference between the two inputs. Could you please comment on that?

The following sinusoidal signals, sin(ω₁t) and sin(ω₂t), have different frequencies but the phase is same.
These signals, sin(ω₁t+φ₁) and sin(ω₂t+φ₂), have different frequencies and phases.
These signals, sin(ω₁t+φ₁) and sin(ω₁t+φ₂), have same frequencies but different phases.

Thank you!

 

[ronsimpson]

I use the 4046 PLL. It has three different types of phase comparators. The one I use the most is the "edge lock loop" that tries to put the rising edges together. It does not care about the falling edge, or the duty cycle.

I have use a phase comparator where if the phase is 180 off the voltage is 0. At 0 degrees the voltage is 1/2 supply. Then at -180 off the voltage is at supply. The VCO might need a 0V or near full supply to get the right frequency. Bottom line is the phase shifts. (the signal needs to be 50/50 duty cycle)

An edge lock loop can make a error voltage of 0 to supply with out any phase error.

There are many different type of phase comparators.

 

[Diver300]

Thanks a lot, everyone!

Now I'm really confused about the function of phase comparator. I had thought that the output of the phase detector is a voltage proportional to the phase difference between the two inputs but from your reply it seems more like if the output of the phase detector is a voltage proportional to the frequency difference between the two inputs. Could you please comment on that?

It's a phase detector, so the output is proportional to the phase difference.

If there is a frequency difference, the phase difference will not be constant, and will get larger and larger over time. As the phase difference gets larger, the signal to the VCO gets larger, so the frequency gets larger which reduces the frequency difference, so the phase changes more slowly, until eventually there is a constant phase difference and no frequency difference.

(Most phase locked loops can start off going the wrong way. When the phase difference gets to 180 degrees, it has to start reducing, so the direction automatically reverses).

 

[PG1995]

Thank you!

If there is a frequency difference, the phase difference will not be constant, and will get larger and larger over time. As the phase difference gets larger, the signal to the VCO gets larger, so the frequency gets larger which reduces the frequency difference, so the phase changes more slowly, until eventually there is a constant phase difference and no frequency difference.

So, once the frequency difference gets null, the phase difference becomes a constant value. In other words, in the context of a PLL, the phase difference between, for example, two sinusoidal signals with different frequencies will continuously vary. Or, we can say it gets larger over time as Diver300 pointed out. But the question is 'how'.

Let me try.

The frequency of v1 is greater than v2. Both signals starts at the same time but v1 completes its cycle first so it creates a phase difference, φ₁ . So, for v1, the second cycle would take the same time to complete but this time phase difference would be even more, i.e. φ₂ > φ₁, because for the second cycle the signals don't even start together. The phase difference could not be 180 degrees or more because then it becomes a confused state and we might say that v1 is lagging v2. Do I make sense? Thank you.

 

[Nigel Goodwin]

Now I'm really confused about the function of phase comparator. I had thought that the output of the phase detector is a voltage proportional to the phase difference between the two inputs but from your reply it seems more like if the output of the phase detector is a voltage proportional to the frequency difference between the two inputs. Could you please comment on that?

In common with many posts on here, you're over thinking it - in practice frequency and phase are effectively the same thing - and in this case you're not interested in the phase relationship, only the frequency relationship. You can use phase modulation or frequency modulation for FM transmitters, both give exactly the same result - and many of the older 2m radio transmitters actually used phase modulation to create the frequency modulation.

 

[JimB]

Now I'm really confused about the function of phase comparator. I had thought that the output of the phase detector is a voltage proportional to the phase difference between the two inputs but from your reply it seems more like if the output of the phase detector is a voltage proportional to the frequency difference between the two inputs. Could you please comment on that?

In practice that is what happens.
After the LPF the control signal to the VCO is a steady DC signal.
If the loop were to be out of lock, that DC signal would rise up to the supply voltage, or, it would drop to zero depending on whether the unlocked frequency of the oscillator was above or below the frequency required for lock.

In common with many posts on here, you're over thinking it

Agreed.

JimB

 

[PG1995]

Hi,

Could you please help me with the queries below? I understand that you might find it frustrating that I'm asking questions about the same topic but I'm only struggling to get a proper understanding of it. Thank you!

Please have a look on the attachment.

Question 1:
I don't really understand where it says, "The two frequencies cause the phase difference to be a beat behaviour". What does it mean? Is it suggesting that two different frequencies cause beat behavior where 'beat' might suggest oscillation.

Question 2:
It says, "The average output is zero if ω1≠ω2". What does it mean? Is it saying that average output of phase detector is zero? If the average output of phase detector is really zero then VCO would keep on oscillating with its free-running frequency which is not possible in case of ω1≠ω2.

 

[Diver300]

Hi,

Could you please help me with the queries below? I understand that you might find it frustrating that I'm asking questions about the same topic but I'm only struggling to get a proper understanding of it. Thank you!

Please have a look on the attachment.

Question 1:
I don't really understand where it says, "The two frequencies cause the phase difference to be a beat behaviour". What does it mean? Is it suggesting that two different frequencies cause beat behavior where 'beat' might suggest oscillation.

Question 2:
It says, "The average output is zero if ω1≠ω2". What does it mean? Is it saying that average output of phase detector is zero? If the average output of phase detector is really zero then VCO would keep on oscillating with its free-running frequency which is not possible in case of ω1≠ω2.

Q1. By a "beat" frequency, what is meant is the frequency difference. In this case, if you have one frequency of 100 Hz, and one of 101 Hz, the phase difference between the two will take 1 second to go from 0 degrees (in phase) though 180 degrees (totally out of phase) and back to 360 degrees, or zero degrees, and back in phase again.

Q2. If the two frequencies continue to differ, so ω1≠ω2, then the output of the phase detector will continually vary from maximum (at 0 degrees phase difference) to minimum (at 180 degrees phase difference). If the phase detector has a maximum that is positive and a minimum that is negative by the same amount, then the average output will be zero.

A phase locked loop relies on the frequencies being close enough that the phase detector output is high or low for a long enough time that the VCO frequency can change enough to actually achieve phase lock. It is very common to have a PLL where both the reference and the VCO frequencies are divided, to give enough time for a lock. If I have a 1 MHz reference, and a VCO that gives me 0.8 - 1.2 MHz, when the VCO is at maximum or minimum, the frequency difference is 200 kHz, so the phase comparator output will only be above zero for 2.5 microseconds, an the VCO might well not be able to respond that fast.

If both frequencies were divided by 1000, the phase comparator output will be high for 2.5 milliseconds.

I think that an analogy of a phase locked loop would be good. Imagine you are driving on the highway, and in another lane there are some identical cars to your, running in convoy. For some reason, you want to get your engine speed to be the same as the ones in convoy. So you adjust your speed to match a car in the convoy, by accelerating when you are behind the nearest car or decelerating when you are in front of the nearest car.

If that works, you end up near one car, going at the same speed, and the average speed of your car's engine matches those of the cars in the convoy, so you have a phase locked loop.

The ω1≠ω2 is where the position of the other cars is ignored, and the speed is different. The beat frequency is how fast you are passing the other cars, which will be a lot slower than you would be passing fixed objects.

The phase detector equivalent is whether you are in front or behind the nearest car. If the speed / position of the other cars is being ignored, then you will spend just as much time in front (positive) of whichever car is nearest as you will behind (negative) whichever car is nearest, so the average distance in front will be 0.

 

[PG1995]

Thank you so much! Your reply is really helpful.

Q2. If the two frequencies continue to differ, so ω1≠ω2, then the output of the phase detector will continually vary from maximum (at 0 degrees phase difference) to minimum (at 180 degrees phase difference). If the phase detector has a maximum that is positive and a minimum that is negative by the same amount, then the average output will be zero.

It's a phase detector, so the output is proportional to the phase difference.

Wouldn't it be maximum when the input frequencies are 180 degrees out of phase and minimum when they are in phase?

I don't understand how expression 3.49 shown below is reached in this text from my previous post. Could you please have a look at it?

I tried it but couldn't proceed any further.

 

[Diver300]

Thank you so much! Your reply is really helpful.

Wouldn't it be maximum when the input frequencies are 180 degrees out of phase and minimum when they are in phase?

It depends on the particular phase comparator. In most PLLs it doesn't matter which way round the phase comparator works. One way round will end up with the phase of the VCO being in advance of the reference signal, the other will end up with the VCO lagging the reference signal. The frequencies will end up the same either way. I hadn't worried about the direction of operation in my post.

If the mid output of the phase comparator is at +90 degrees and at -90 degrees, and the VCO is at the right frequency when the phase comparator output is at mid output, then either +90 or -90 phase difference will be stable, and the other won't be.

 

[Diver300]

Thank you so much! Your reply is really helpful.
I don't understand how expression 3.49 shown below is reached in this text from my previous post. Could you please have a look at it?

I tried it but couldn't proceed any further.

There is a slight mistake in the conditions for equation 3.48. The A2 term should use omega2 not omega (and I can't find how to Greek characters and subscripts).

In your equation, you get to the sum of a cosine of twice the frequency, the bit highlighted in yellow, which isn't in equation 3.49. That bit in yellow is correct, but for a phase comparator, it is irrelevant. The output of a phase comparator will be filtered to give only the low frequency components, so components at twice the frequency are ignored. What is left is a voltage that only depends on phase. The text before equation 3.49 says "the phase voltage characteristic is", so the high frequency terms are ignored.

It is typical of a frequency mixer / phase comparator to output the sum of the frequencies and the difference between them. In a phase locked loop, only the difference is of interest, and higher frequencies are filtered out.

 

[PG1995]

Thank you very much!

Question 1:
It looks like, at least according to some of the references I have been through, when a PLL is locked the input/reference frequency and output frequency which is coming out of VCO are the same but the phase difference between them would be 90 degrees. In other words, when the phase difference is 90 degrees, it is said that the phase difference is zero.

"The goal is to generate a VCO output whose frequency is the same as the frequency of the received signal and phase is different from the phase of the received signal by 90 degrees."
[Introduction to Digital Communications, Ali Grami, 2016 edition, PDF page #369]

By the way, is there any reason that why the 'inherent' phase difference is 90 degrees and not simply 0 degrees? One reason might be that it's more easier to implement with 90 degrees phase difference rather than going 0 degrees.

Question 2:
The following text is taken from this attachment. The difference between the two definitions is seemingly so subtle that the definition of Capture Range eludes the understanding.

Lock Range
The lock range of a PLL is the range of input frequencies over which the VCO can remain locked onto and track the input frequency. It is related to the maximum phase difference that can be detected. In our discussion, we are assuming that the phase detector can produce an output voltage for Δφ between -90° and +90°. At these limits, the phase detector produces a maximum output voltage, either negative or positive.

If the input frequency is too low or too high, the phase difference is outside the range of -90° and +90°. Therefore, the phase detector cannot produce the additional voltage needed for the VCO to remain locked on. At these limits, therefore, the PLL loses its lock on the input signal.

The lock range is usually specified as a percentage of the VCO frequency. For instance, if the VCO frequency is 10 kHz and the lock range is +/-20%, the PLL can remain locked on any input frequency between 8 and 12 kHz.

Capture Range
The capture range is different. Assume that the input frequency is outside the lock range. Then, the VCO is free running at 10 kHz. Now, assume that the input frequency changes toward the VCO frequency. At some point, the PLL will be able to lock onto the input frequency. The range of
input frequencies within which the PLL can reestablish the lock is called the capture range.

The capture range is specified as a percentage of the free running frequency. If f_0=10 kHz and the capture range is +/-5%, the PLL can lock on to an input frequency between 9.5 and 10.5 kHz. Typically, the capture range is less than the lock range because the capture range depends on the cutoff frequency of the low-pass filter. The lower the cutoff frequency, the smaller the capture range.

The cutoff frequency of the low-pass filter is kept low to prevent high-frequency components like noise or other unwanted signals from reaching the VCO. The lower the cutoff frequency of the filter, the cleaner the signal driving the VCO. Therefore, a designer has to trade off capture range against low-pass bandwidth to get a clean signal for the VCO.

Source: https://www.quora.com/What-is-lock-range-and-capture-range-of-phase-locked-loop-in-simple-terms



Notes to self:
1: In the picture you can see that the signals in black and red have the frequency but have 90 degrees phase difference. Their phase difference remains constant. The signal in green has a different frequency and is phase shifted by 90 degrees like the signal in red. You can see that its phase relationship keeps on changing with both other signals. Compare the peaks. It means if the frequency is same, the phase remains constants otherwise it varies. Two signals with different frequencies cannot have constant phase relationship

2: "The phase detector on these devices is a digital circuit that responds to the rising edges of the detector’s two inputs. The phase detector output has three states: a high, 5V state, a low, 0V state, and a middle, 2.5V state. In the high and low states the output impedance of the detector is low and the middle state output impedence is high, typically 6.0kW. When there is any static frequency difference between the inputs, the detector output is fixed at its high level if the +input (the sense amplifier signal) is greater in frequency, and fixed at its low level if the -input (the reference frequency signal) is greater in frequency.

When the frequencies of the two inputs to the detector are equal, the phase detector switches between its middle state and either the high or low states, depending on the relative phase of the two signals. If the +input is leading in phase then, during each period of the input frequency, the detector output will be high for a time equal to the time difference between the rising edges of the inputs, and will be at its middle level for the remainder of the period. If the phase relationship is reversed, then the detector will go low for a time proportional to the phase difference of the inputs."
[https://drive.google.com/file/d/1w0vrga2LnCQb-osBQj3PH-aUzZCW583Q/view?usp=sharing , Page #5]

3: This reference is really good and has detailed mathematical analysis of PLL
[https://drive.google.com/file/d/1TN9ILumjvNui0hJtMCxLQ3xFjiySJu8p/view?usp=sharing]

4: This reference is also really good with important details
[https://drive.google.com/file/d/13K6EQcZSQSCmOsO2STgsgMK5wD_SKPI9/view?usp=sharing]

5: "Phase detectors for phase-locked loop circuits may be classified in two types.[1] A Type I detector is designed to be driven by analog signals or square-wave digital signals and produces an output pulse at the difference frequency. The Type I detector always produces an output waveform, which must be filtered to control the phase-locked loop voltage-controlled oscillator (VCO). A type II detector is sensitive only to the relative timing of the edges of the input and reference pulses, and produces a constant output proportional to phase difference when both signals are at the same frequency. This output will tend not to produce ripple in the control voltage of the VCO. "
[https://en.wikipedia.org/wiki/Phase_detector#Types]

6: "Phase Locked Loops (PLL) circuits are used for frequency control. They can be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits. Each of these applications demands different characteristics but they all use the same basic circuit concept. Figure 1 contains a block diagram of a basic PLL frequency multiplier. The operation of this circuit is typical of all phase locked loops. It is basically a feedback control system that controls the phase of a voltage controlled oscillator (VCO). The input signal is applied to one input of a phase detector. The other input is connected to the output of a divide by N counter. Normally the frequencies of both signals will be nearly the same. The output of the phase detector is a voltage proportional to the phase difference between the two inputs. This signal is applied to the loop filter. It is the loop filter that determines the dynamic characteristics of the PLL. The filtered signal controls the VCO. Note that the output of the VCO is at a frequency that is N times the input supplied to the frequency reference input. This output signal is sent back to the phase detector via the divide by N counter. Normally the loop filter is designed to match the characteristics required by the application of the PLL. If the PLL is to acquire and track a signal the bandwidth of the loop filter will be greater than if it expects a fixed input frequency. The frequency range which the PLL will accept and lock on is called the capture range. Once the PLL is locked and tracking a signal the range of frequencies that the PLL will follow is called the tracking range. Generally the tracking range is larger than the capture range. The loop filter also determines how fast the signal frequency can change and still maintain lock. This is the maximum slewing rate. The narrower the loop filter bandwidth the smaller the achievable phase error. This comes at the expense of slower response and reduced capture range. "
[https://electricalelctronic.blogspot.com/2012/02/phase-locked-loop-pll.html ]

7: https://www.electronics-tutorial.net/analog-integrated-circuits/phase-locked-loop/pll-applications/

8: https://www.cardinalxtal.com/static/frontend/files/cardinal-phase-lock-loop-basics.pdf

9: https://en.wikipedia.org/wiki/Phase-locked_loop

10: https://imagizer.imageshack.com/img923/5011/gcLlz7.jpg

11: https://www.idc-online.com/technical_references/pdfs/electronic_engineering/Phase_Locked_Loop.pdf

 

[Diver300]

Thank you very much!

Question 1:
It looks like, at least according to some of the references I have been through, when a PLL is locked the input/reference frequency and output frequency which is coming out of VCO are the same but the phase difference between them would be 90 degrees. In other words, when the phase difference is 90 degrees, it is said that the phase difference is zero.

"The goal is to generate a VCO output whose frequency is the same as the frequency of the received signal and phase is different from the phase of the received signal by 90 degrees."
[Introduction to Digital Communications, Ali Grami, 2016 edition, PDF page #369]

By the way, is there any reason that why the 'inherent' phase difference is 90 degrees and not simply 0 degrees? One reason might be that it's more easier to implement with 90 degrees phase difference rather than going 0 degrees.

If a PLL is being used to lock a VCO to a reference frequency, it is usual for the actual phase difference to be unimportant. It is only the frequency that matters.

A voltage multiplier, or an XOR gate can be used as a phase comparator, and they will often give a maximum output at 180 or at 0. The mid output will be at 90 degrees or -90 degrees and so that will be the design point. It is more difficult to make a phase comparator that gives mid output at 0 degrees difference, and if the frequency is the only output of interest, it's pointless as well.

The phase comparator output will vary around the mid point as the input frequency varies, or temperature or other things affect the VCO. As a result of these variations, the phase will vary a bit as well.

 

[Diver300]

Question 2:
The following text is taken from this attachment. The difference between the two definitions is seemingly so subtle that the definition of Capture Range eludes the understanding.

Lock Range
The lock range of a PLL is the range of input frequencies over which the VCO can remain locked onto and track the input frequency. It is related to the maximum phase difference that can be detected. In our discussion, we are assuming that the phase detector can produce an output voltage for Δφ between -90° and +90°. At these limits, the phase detector produces a maximum output voltage, either negative or positive.

If the input frequency is too low or too high, the phase difference is outside the range of -90° and +90°. Therefore, the phase detector cannot produce the additional voltage needed for the VCO to remain locked on. At these limits, therefore, the PLL loses its lock on the input signal.

The lock range is usually specified as a percentage of the VCO frequency. For instance, if the VCO frequency is 10 kHz and the lock range is +/-20%, the PLL can remain locked on any input frequency between 8 and 12 kHz.

Capture Range
The capture range is different. Assume that the input frequency is outside the lock range. Then, the VCO is free running at 10 kHz. Now, assume that the input frequency changes toward the VCO frequency. At some point, the PLL will be able to lock onto the input frequency. The range of
input frequencies within which the PLL can reestablish the lock is called the capture range.

The capture range is specified as a percentage of the free running frequency. If f_0=10 kHz and the capture range is +/-5%, the PLL can lock on to an input frequency between 9.5 and 10.5 kHz. Typically, the capture range is less than the lock range because the capture range depends on the cutoff frequency of the low-pass filter. The lower the cutoff frequency, the smaller the capture range.

The cutoff frequency of the low-pass filter is kept low to prevent high-frequency components like noise or other unwanted signals from reaching the VCO. The lower the cutoff frequency of the filter, the cleaner the signal driving the VCO. Therefore, a designer has to trade off capture range against low-pass bandwidth to get a clean signal for the VCO.

Source: https://www.quora.com/What-is-lock-range-and-capture-range-of-phase-locked-loop-in-simple-terms

Let's assume that the phase detector has a maximum output at 180 and a minimum output at 0.

If the PLL is locked, and the frequency is in the middle, the phase difference will be 90.

Now the reference frequency increases. The phase difference increases, so the phase detector output increases, the VCO frequency increases and lock is maintained. Now the phase difference is larger, say 120 degrees, and the phase detector output is above mid, but below maximum. So far, so good. It's being a PLL.

Now increase the reference frequency more. The phase difference increases, the phase detector output increases. Eventually the phase will approach 180 degrees and the phase detector output will be near the maximum. The PLL is still working, but it's on its limit, and it is at one end of the lock range. That is the maximum lock frequency.

Now turn off the reference frequency. The phase comparator produces a mid voltage and the VCO moves to the mid frequency. Now turn on the reference frequency again, as the maximum lock frequency. The phase comparator will start producing a sine-ish wave, varying between minimum and maximum at around the difference between the mid frequency and the maximum lock frequency.

Although the VCO frequency is changing, it never quite gets to the maximum lock frequency because the phase comparator output is never stable at the maximum voltage for any length of time, and any filtering at all will stop there being a lock.

The reference frequency needs to be reduced a bit, to give the phase comparator and VCO a bit of time, in the cycle of phase comparator output waveform, to get to the right frequency. When that is done, the top of the capture range has been found.

 

[Beau Schwabe]

Another way to multiply or divide the frequency is to use a second PLL. The first PLL is still used in the same way to lock the feedback loop. On the second PLL you just use the VCO portion and level shift the voltage from the output of first PLL with an Op-Amp to the input of the second PLL so that the desired frequency is obtained. This avoids the digital step from the divide by N counter and provides a more dynamic response if the input frequency changes which may or may not be desirable.