Peer review requested: analog timer circuit

[earckens]

Hi, following design has the purpose to transmit a low to high transition with delay to the output.
The delay is set by R7 and C3.
The 555 functions as a monostable multivibrator: the input transition (L -> H) is transformed to a pulse (C1 and R3) which triggers pin 2 which sends pin 3 high which sends Q3 conducting which keeps Q1 non-conducting.
As soon as the C3/R7 time has lapsed pin 3 goes low and allows the output to go high.

My question concerns the values for R1 and R5: I think these can be optimised, but I would like your opinion on this?

In particular when IC2 is conducting output 4 is presented R1 and R5 in parallel to ground when Q3 is conducting (not an issue by itself), but when Q3 opens, then the gate of Q1 may see a voltage divider of the 12V supply to ground. Since this is an N-channel with load to source, the gate voltage does matter.

 

[eTech]

Hi

Looks like the circuit could be simplified some.
Why the opto?
Depending on the load, It may not need Q1 and Q3.

eT

 

[AnalogKid]

A couple of things.

With a 2N7000 operating as a source follower, the output will a couple of volts less than the system +12 V due to the FETs threshold voltage.

If the input goes low during the timer period, the output never will go high.

Once the timer period is over and the output is high, it will stay high only as long as the input is high. When the input goes low, the output goes low immediately.

Is the opto coupler required for input isolation?

For a long timer period like this, I recommend a CMOS 555 - LMC555.

If what you want is a circuit that delays the leading edge of a pulse, but not the trailing edge, there are much less complex circuits for that. For example, a single AND gate plus 1 R-C will do everything you describe. However, with the long, slow timing voltage ramp, I recommend the CD4093 NAND gate with Schmitt Trigger inputs; two gates, one for the logic and one to correct the output polarity. Another way uses no chips, just two transistors.

ak

 

[earckens]

A couple of things.

With a 2N7000 operating as a source follower, the output will a couple of volts less than the system +12 V due to the FETs threshold voltage.

That is why I wonder if R1 and R5 are correctly dimensioned

If the input goes low during the timer period, the output never will go high.

The input will, due to the nature of the circuit before the optocoupler, never be triggered during the timer period
EDIT: for good understanding: pin 2 receives a high pulse, triggering pin 3 to go high during the R7/C3 time

Once the timer period is over and the output is high, it will stay high only as long as the input is high. When the input goes low, the output goes low immediately.

When the timer period is over pin 3 goes low; when pin 2 is triggered again pin 3 will go high again; that is the purpose too

Is the opto coupler required for input isolation?

Yes, the circuit before the optocoupler requires isolation

For a long timer period like this, I recommend a CMOS 555 - LMC555.

Why?

If what you want is a circuit that delays the leading edge of a pulse, but not the trailing edge, there are much less complex circuits for that. For example, a single AND gate plus 1 R-C will do everything you describe. However, with the long, slow timing voltage ramp, I recommend the CD4093 NAND gate with Schmitt Trigger inputs; two gates, one for the logic and one to correct the output polarity. Another way uses no chips, just two transistors.

ak

Can you show me a circuit with the CD4093?

The nice thing about the 555 is that it is so versatile, and it costs me about 3 eurocent; the cd4093 comes at about 6 eurocent (quantities of 100, free delivery).

 

[AnalogKid]

How many circuits will you be building? If multiple circuits are closely spaced, an advantage of the 4093 is that you get two circuits in one 14-pin package. With a hex inverter and some diodes you get three circuits in one 14-pin package.

A 1 M timing resistor means that the capacitor charging current varies between 12 uA and 4 uA. Depending on the quality of the capacitor, its leakage current might be a significant percentage of the charging current, upsetting the standard timing equation. Also, the bipolar 555 has inputs currents that contribute error. The CMOS part has extremely high input impedances, eliminating some of the errors and allowing and even larger timing resistor, which allows a smaller timing capacitor. The timing capacitor is the largest source of error in your circuit. Besides its poor initial tolerance, its value changes with age, temperature, phase of the moon, etc.

For timing periods over a few seconds I prefer a counter-based circuit. The timing components can be much smaller and more precise. Also, a counter resets instantly so there is no capacitor reset time or high discharge current.

ak

 

[earckens]

Hi AnalogKid, very interesting your counter concept. Also thanks for the cmos 555 explanation!

Besides that, what is your take on the values for R1 and R5 in this circuit's context?

 

[AnalogKid]

Besides that, what is your take on the values for R1 and R5 in this circuit's context?

They are fine. For commonality of parts in a production environment, I might change R4 and R5 to 10K. What is the IC2 input current?

ak

 

[ronsimpson]

Opto isolator has R2 68k to ground. I think the transistor will never turn on.
Maybe you want the resistor from B-E not Base to ground. (big difference)

 

[earckens]

How many circuits will you be building? If multiple circuits are closely spaced, an advantage of the 4093 is that you get two circuits in one 14-pin package. With a hex inverter and some diodes you get three circuits in one 14-pin package.

This circuit is part of a quite larger circuit, so this circuit remains singular.

A 1 M timing resistor means that the capacitor charging current varies between 12 uA and 4 uA. Depending on the quality of the capacitor, its leakage current might be a significant percentage of the charging current, upsetting the standard timing equation. Also, the bipolar 555 has inputs currents that contribute error. The CMOS part has extremely high input impedances, eliminating some of the errors and allowing and even larger timing resistor, which allows a smaller timing capacitor. The timing capacitor is the largest source of error in your circuit. Besides its poor initial tolerance, its value changes with age, temperature, phase of the moon, etc.

Thanks for that input, very useful.

For timing periods over a few seconds I prefer a counter-based circuit. The timing components can be much smaller and more precise. Also, a counter resets instantly so there is no capacitor reset time or high discharge current.
ak

Good to know. Luckily in this design timing accuracy is no issue, the timer may be off, drift and change, as long as it will not change by more than 50%. I set the timing at about 30 seconds, if it changes to 45 seconds or 15 seconds that is ok in this particular case.

 

[earckens]

Opto isolator has R2 68k to ground. I think the transistor will never turn on.
Maybe you want the resistor from B-E not Base to ground. (big difference)

Very good point! Thank you; design will be adapted.

 

[earckens]

(...) What is the IC2 input current?

ak

What do you mean? The actual measured current consumption?

 

[AnalogKid]

What is the peak input voltage to the optocoupler diode? Or, what is the current through R9 when the input is high?

ak

 

[earckens]

What is the peak input voltage to the optocoupler diode? Or, what is the current through R9 when the input is high?

ak

45mA

 

[AnalogKid]

A surprisingly high value, but more than enough to assure that the output transistor is saturated.

R1 and R5 are a tradeoff between transistor current and noise control. The larger the resistors, the lower the opto transistor current. But the larger the resistors, the higher the gate impedance to GND when the IC2 and Q3 transistors are off, and the higher that impedance is the more susceptible Q3 is to radiated noise. Life is choice.

ak