PC based oscilloscope topology

[renzen]

Many oscilloscope projects in the web, makes me want to know the topology of pc based oscilloscope. After I read and a little study, the topology approximately like this(please correct me if I'm wrong),
- ADC convert input data and convert to binary code(square signal). The bigger sampling rate will gives higher resolution(like dpi in picture format).
- ADC sent the output to microcontroller or FPGA. From microcontroller or FPGA, sent data to PC via serial, USB, PCI, or PCI express(fiber optics?). If the data is high but the connection to pc is slow, data save in microcontroller or FPGA memory.
- PC program process the data to graphic.
Is this correct?

My question:
- When ADC sent the binary code(square signal) output to microcontroller analog input, does the microcontroller do converting process again?
- If using FPGA, FPGA can stand alone or need a microprocessor?

Thank you and sorry for my poor English

 

[MrAl]

Hello,

The ADC converts the analog to digital. It stays digital after that. If it is sent to a microcontroller it is sent in digital form.

The resolution is dependent on two main things:
1. The analog resolution of the ADC.
2. The speed of the ADC.

The analog resolution allows for more samples per volt, while the speed allows more samples per second.

 

[renzen]

Another question,

Someone bought a FPGA devlopment kit with oscilloscope module. After he tested it, it's not working because missing a file(development kit didn't provide it). In some way, he succeed to make it run. He assumed the FPGA devlopment kit is quite warm because it's sampling at 250m times in a second.
This make me confuse, because I assumed FPGA only control data flow(sending data to PC or read/write data to memory), and sampling process is in ADC.
So, is there a process in FPGA? If there's a process in FPGA, what process will make the FPGA warm?

 

[MrAl]

Hello again,

The ADC does the analog sampling at the maximum clock rate that works for that particular ADC. It can be 20MSPS, 50MSPS, or 100MSPS, even 1GSPS or higher. That means that the data being sent OUT of the ADC might be coming out at 250MBPS (250 megabytes per second). Something has to process this even though it is in digital form, and if that is a FPGA then it must handle 250MBPS input anyway.

Now when a clock or data signal changes from 0 to 1 or from 1 to 0, it must charge or discharge a capacitor. Because of the impedances, that means it takes a certain time trise or tfall to change state. In that time the resistance part of the impedance absorbs a certain amount of energy E. This state transition energy is fairly constant independent of clock speed or buss speed, but as the clock or buss speed is increased, this energy is dissipated more often. As the clock speed is increased, the transition period stays about the same while there are more of them, so the total power dissipation goes up. This is one of the problems with any high speed logic design, more notable modern CPU's. There is a point that is reached where the surface area of the package can not dissipate the required power being dissipated internally, so the package begins to heat up above the normal operating temperature. If the situation continues, the package could burn up.
The equation looks very roughly like this:
TemperatureRise=K*(P/A)^0.8

where K is a constant, P is the total power, A is the total surface area, TemperatureRise is the rise above ambient.

So while the ADC has to run at the clock speed, so does any associated glue logic and even logic dissipates power mostly because of the state transition period which causes more and more power dissipation as the clock speed is increased.

You can simulate this by charging and discharging a small capacitor through a resistor, and computing or looking at the average power dissipated in the resistor over say 1000 cycles.
The frequency should be low enough to allow the cap to completely charge or discharge, or at least to say 99 percent.
As the frequency is increased, the total power goes up. At some point the frequency will be too high to allow proper charge and discharge but that is beyond a normal operating frequency so that doesnt count.
If we let the cap charge for at least 5 time constants, then an estimate of the total average power is:
Pavg=RC/(2*T)
where
RC is the resistance times the capacitance,
T is the total period between charge and discharge cycles (square wave excitation).

 

[ChrisP58]

There are also other functions of the oscilloscope that will likely be done by an fpga.

• Averaging. If the ADC can sample faster than the selected sweep rate requires, then the fpga may average 2 or more samples for each display point. This results in a smoother display.
• Triggering. The fpga would be looking at each result of the ADC to see if the trigger criteria has been meet.
• Pre-trigger data. A big plus with digital scopes is the ability to capture and store information before the trigger event. This will require the fpga and it's memory to save all samples. Then, when the trigger event occurs, to shift that data around to time correlate the data to the screen.
• Doing math functions with data from two or more channels. Example: Subtracting CH-B from CH-A to give a third trace that is the difference of the two.
• Measurements. Calculating rise/fall time, period, frequency, duty cycle, RMS value, peak value, peak to peak value. etc. And when those measurements are made. forming the dots to make the words and numbers appear within the scope display field.

I'm sure that there are more tasks that may use the fpga. This is from a quick think.