Hello again,
The ADC does the analog sampling at the maximum clock rate that works for that particular ADC. It can be 20MSPS, 50MSPS, or 100MSPS, even 1GSPS or higher. That means that the data being sent OUT of the ADC might be coming out at 250MBPS (250 megabytes per second). Something has to process this even though it is in digital form, and if that is a FPGA then it must handle 250MBPS input anyway.
Now when a clock or data signal changes from 0 to 1 or from 1 to 0, it must charge or discharge a capacitor. Because of the impedances, that means it takes a certain time trise or tfall to change state. In that time the resistance part of the impedance absorbs a certain amount of energy E. This state transition energy is fairly constant independent of clock speed or buss speed, but as the clock or buss speed is increased, this energy is dissipated more often. As the clock speed is increased, the transition period stays about the same while there are more of them, so the total power dissipation goes up. This is one of the problems with any high speed logic design, more notable modern CPU's. There is a point that is reached where the surface area of the package can not dissipate the required power being dissipated internally, so the package begins to heat up above the normal operating temperature. If the situation continues, the package could burn up.
The equation looks very roughly like this:
TemperatureRise=K*(P/A)^0.8
where K is a constant, P is the total power, A is the total surface area, TemperatureRise is the rise above ambient.
So while the ADC has to run at the clock speed, so does any associated glue logic and even logic dissipates power mostly because of the state transition period which causes more and more power dissipation as the clock speed is increased.
You can simulate this by charging and discharging a small capacitor through a resistor, and computing or looking at the average power dissipated in the resistor over say 1000 cycles.
The frequency should be low enough to allow the cap to completely charge or discharge, or at least to say 99 percent.
As the frequency is increased, the total power goes up. At some point the frequency will be too high to allow proper charge and discharge but that is beyond a normal operating frequency so that doesnt count.
If we let the cap charge for at least 5 time constants, then an estimate of the total average power is:
Pavg=RC/(2*T)
where
RC is the resistance times the capacitance,
T is the total period between charge and discharge cycles (square wave excitation).