I see your problem now, you simply forgot how NMOS voltage follower work.I have been reading a lot about using NMOS and PMOS in LDO. However, I am still
confused about the dropout voltage calculation in each case.
Are you sure about that ?In your picture, it is a common source topology.
This error amplifier is nothing more than the ordinary op amp. And every op amp has his on output voltage range. And for the typical op amp the maximum positive voltage output voltage is 1V smaller then Vcc.1. In your example, the gate G is connected to Vin. However, in LDO, it is connected with the output of error amplifier. That makes the calculation more difficult. If G is connected with the output of error amplifier, how would you calculate the dropout voltage, Vdrop = Vds, there?
Yes, I know that. The current through PMOS increased significantly as the voltage Vsg increases a little.First, a PMOS is driven from the ground up, such that the closer the gate is to ground the more it conducts.
Vin = VsThat means as long as there is input voltage there is always enough gate voltage available.
But for NMOS there is not always enough gate drive available because the gate has to be higher than the source, and if the source is already very close to the drain (the drain gets the input voltage level applied to it, which is the maximum available voltage in the system) this means the gate voltage will always be lower than the level needed to drive the NMOS source very very close to the input voltage level (that's LDO operation).
I see your problem now, you simply forgot how NMOS voltage follower work.
As a reminder can you tell me what is the output voltage (Vout) in these three simple circuits? You can assume Vgs = 3V
I thought it is PMOS in your picture.Are you sure about that ?
Do you understand this now ?
I meant the error amplifier.Hi,
What amplifier?
I am talking about the one on the left. It is LDO.Hi,
Are you talking about the two circuits in post #3 ?
OK, I see.The total gain for that circuit is made of the op amp and the PMOS.
The voltage gain of the op amp is usually high and varies, but if it's a fixed value then you calculate the approximate gain of the op amp plus PMOS by noting that the transconductance leads to a current output but then the resistive load makes that a voltage value. Knowing the gm and the output circuit resistance you can then calculate the voltage gain of the PMOS stage and multiply that by the gain of the op amp.
Now knowing the gain, we would then proceed to calculate the output voltage Vout knowing the reference voltage, doing the full loop not open loop. This gives us a fixed value for the output voltage Vout which we can then compare to Vref. This then gives us a way to measure the quality of the circuit to regulate the output voltage to within some percentage from ideal.
As a simple example, say we have a reference voltage of 1.0 volt. Then after we calculate the gain of the PMOS stage and combine it with the op amp gain and then calculate the full loop so we get the output voltage result say we see 0.9 volts. This result is rather poor being 10 percent off, so we know we dont have enough gain in the op amp and/or PMOS section. If we got 0.95 volts it still isnt that good. If we got 0.99 volts then it's much better now. However, to get 0.95 instead of 0.90 meant we had to put in more gain, and getting 0.99v rather than 0.95 meant we had to add even more gain yet.
It would be great if you could explain more about this.A couple things to note:
1. The PMOS adds a lot of voltage gain to the loop which helps the steady state error.
2. With a voltage follower circuit if the gain is infinite the output voltage matches the input exactly (or some ratio exactly set by the resistors).
To get an understanding of the PMOS we can start with the simplified model where we have a zero gate threshold and no capacitance. The output current is then just dependent on the absolute gate voltage (gate voltage measured source to drain). The output current is then simply:
Iout=gm*Vg
so if we have a gm of 0.1 and a gate voltage of 2 volts we have Iout=0.1*2=200ma.
Now with a resistive load that is much lower than the divider resistors R1 and R2, we have Rout=Rload, but with no load we have only R1 and R2 in series so we would have Rout=R1+R2.
With either of these conditions, we then have Vout=Iout*Rout where Iout is from above.
Since Iout=gm*Vg with this simplified model we then have Vout=gm*Vg*Rout. This leads to the gain:
A2=gm*Rout (although it is actually an inverter so it would be negative)
So the total gain is A1*A2=A1*gm*Rout.
Note we have not yet considered any output capacitance, gate capacitance, or gate threshold voltage. The gate threshold voltage puts a requirement on the A1 gain because we have to have enough gain to get the op amp to be able to ramp up (or down) to whatever gate voltage that is required to start the PMOS conducting. So there is a little interplay there in the real world circuit.
Are you starting to see how this works now?
We've only used a resistive load but if the load contained capacitance then we have to start looking at the circuit in terms of frequency response and maybe time domain response as the article did. That is how we could investigate stability.
Well you are pretty much right there i am happy to say, but there is a catch with the PMOS. With the NMOS (voltage follower) the gain being very large makes the error go to zero or at least near that, and with the PMOS with purely resistive elements we might have to be more careful because we don't always have pure resistance in the load and as you already know the PMOS has capacitance and this can ruin our perfect circuit by making it unstable. That would have to be investigated later too because as you probably know gain is important in feedback amplifiers because with some gains they are stable and with other gains they may not be. In fact to be more thorough i would look at the NMOS more critically too just to make sure.
Yes, it was my mistake. I did mean "source" not "drain".When i said gate voltage i meant gate to source, not gate to drain. The gate voltage is measured from gate to source not gate to drain. That's true of any MOSFET.
I am not sure this. You said that the output voltage goes lower. Do you mean that it is lower than the one as the PMOS is completely OFF?Note that with zero output when we apply Vbg the difference is large so the output of the op amp goes lower
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