hi wuchy
Using my GIF as the reference.
U3 is a non inverting buffer for the 5V divider source, providing a low impedance 5V source for U2 and U4.
U2 is configured as a comparator, for Vin and Vref. While Vin < 5V the output of U2 is high holding the non invert input of U1 +5V.
Consider the initial conditions where Vin=0
U1 non invert is fixed at +5V, due the U2 comparator output being high at +5V.
As U1 non inverting gain is 2, the output will be +10V.
This 10V is connected to U4 via by a divide by 2 resistive divider, so U4 has +5V on its non invert input and as U4 has a non invert gain of 2, the output of U4 would tend towards +10V , but as the inverting input is at +5Vref and the invert gain is 1, the output of U4 will be at +5V.....
Consider the condition where Vin has just exceeded the +5Vref and the U2 comparator has switched over, so the input to U1 non invert input is disconnected from the +5Vref, ie: diode D1 is reverse biassed.
The Vin will now be applied to U1 non invert input and as the non invert gain of U1 is 2, the output of U1 will be the algebraic sum of Vin, So the output of U1 will increase from +5V towards +10V as Vin increases.
The output of U1 is divided by 2 and is input to the non invert input of U4, as U4 has an non invert gain of 2, the output of U4 is the algebraic sum of the +5Vref and the divided output from U1.
So the U4 output will ramp up from 0V towards +5V
OK.?