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1) Output sink ability wasn't the question.The LM555 data sheet says, "The output pin can source or sink 200ma".
That data sheet also shows the discharge pin going as high at 100ma with around 1v sat voltage.
No, you are mixed up.1) Output sink ability wasn't the question.
2) We don't know the sat voltage being used. But neither chart (later posted by Eric) goes above 100 mA. 200 mA at 2.5 sat voltage is "off the chart."
No.3) This question was about the NE555, not the LM555. The LM555, while interesting, is off topic, as are the CMOS versions.
No.
The LM555 is the same as an NE555. An LMC555 is a Cmos 555.
National LM555 Datasheet:
https://www.electro-tech-online.com/custompdfs/2011/11/LM555-2.pdf
Philips NE555 Datasheet:
https://www.electro-tech-online.com/custompdfs/2011/11/NE_SA_SE555_C_2-1.pdf
The schematics are not the same.
John
1) Output sink ability wasn't the question.
2) We don't know the sat voltage being used. But neither chart (later posted by Eric) goes above 100 mA. 200 mA at 2.5 sat voltage is "off the chart." In fact, at 5V, the max shown is in accord with the NXP chip.
3) This question was about the NE555, not the LM555. The LM555, while interesting, is off topic, as are the CMOS versions.
Now, I am not saying the NE555 cannot sink 200 mA at the discharge pin. What I am saying to those who claim it can is quite simple. That claim contradicts the manufacturer's datasheet. It contradicts what the manufacturer states about the internal design of the chip. Just show us what you did so the claim can be tested and verified. That is a simple principle applied across science and technology. If you do have data (with the test circuit used) to support that claim -- particularly any data showing long-term stability, heating, and failure rate at the claimed power -- just post it. Again, this thread is about the NE555.
Regards,
John
What dont you understand about the pin 7 current limited only by the package power dissipation?
MrAI said:If you are, on the other hand, looking for low saturation voltage at the discharge pin, then you have to think about limiting the current yourself by design. That's not the same as the max current the transistor can handle. These two specs are different. I think what you are after is a low saturation voltage with some decent current through the discharge pin, which you might not be able to obtain, but you wont burn up the transistor no matter what you do unless you allow it to overheat due to a combination of current and saturation voltage.
You have to also realize that when they designed this thing they made it so that you can connect a largish capacitor right to the discharge pin and the other end to ground. If the discharge pin did not have current protection built in it would burn out on the first cycle pulse the first time it was turned on.
Please try to keep this professional.
I have clearly stated what Philips says about pin7 in the NE555, which differs from what is said about the LM555 in National's datasheet for the LM555. However, if you look at the Fairchild datasheet (https://www.electro-tech-online.com/custompdfs/2011/11/LM555-4.pdf) , you will find a calculation showing the effect of discharge sink capability. In most circuits, it has negligible effect, because external resistance (Ra and Rb) swamp its effect to limit discharge rate. But, it might cause timing differences in circuits where current limiting to 50 mA vs. 200 mA came into play, e.g., if the external resistance is small.
Yes, the datasheet says it is current limited. See my first post in this thread (Post#2). I have no reason to doubt the Philips datasheet for the NE555. You apparently do, based on the National datasheet for the LM555 and your own data, which you for some reason won't show.
John
Thanks, MrAl, but my original post was just seeking design knowledge, with no particular application in mind. A designer might wish to know, for example, if discharging a 1 Farad cap without using an external current-limiting resistor was feasible/safe, or how much time has to be allowed for a cap to discharge before a monostable can be re-triggered.If i knew the application i might be able to recommend something.
Thanks, MrAl, but my original post was just seeking design knowledge, with no particular application in mind. A designer might wish to know, for example, if discharging a 1 Farad cap without using an external current-limiting resistor was feasible/safe, or how much time has to be allowed for a cap to discharge before a monostable can be re-triggered.
You can't design for 'no particular application in mind' if it's not something practical to a specific application then seeking the knowledge itself is pointless except for possibly being a McGuyver'esc trick to use when you don't have the proper components on hand to current bypass a 555 properly.Thanks, MrAl, but my original post was just seeking design knowledge, with no particular application in mind.
Thanks, MrAl, but my original post was just seeking design knowledge, with no particular application in mind. A designer might wish to know, for example, if discharging a 1 Farad cap without using an external current-limiting resistor was feasible/safe, or how much time has to be allowed for a cap to discharge before a monostable can be re-triggered.
Typo error.Also interesting, the Texas Instruments version TL555 (CMOS) states 150ma output OR discharge current limit as an absolute max for the chip. They also give some data for the discharge switch resistance vs supply voltage and temperature.
Thanks for that analysis MrAl.