Multiple flipflop (piano switch)

G

GrahamR

New Member
Hi all.
I thought this would be a straightforward development from a "two-key piano switch", ie an ordinary flipflop, but it's got me baffled, which admittedly doesn't take much.
I can't find anything online. Is it so easy that nobody's bothered posting it? Or am i searching for the wrong thing?
Thanks very much,
 
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A piano switch is normally an on off affair. ( basically a row of switches that look like a piano)

I take it you are attaching to logic to toggle when operated. is this what you are looking for?
 
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Ok, maybe I'm showing my age.

Do you know those mechanical multi-button switches you used to get on radios etc for MW, LW, VHF...? You pressed one button down and the previous one popped up, and so on? They were colloquially called "piano switches". I don't know their actual name, if they had one.

I'm thinking of an electronic version. Obviously an ordinary flipflop will do the same thing as a two-button one. You "press" one side, electrically, and that side stays high while the other side goes low, and vice versa.

I'm trying to think of a "multi-button" flipflop, where "pressing" any stage sends that output high whilst lowering all the others.

Is that clearer?

Thanks,
 
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As far as I'm aware they have never been known as 'Piano switches', as they have no relation to how piano keys work - they are known as 'radio switches', and are even called that in Delphi and Visual Basic etc.

As soon as you use the correct name, loads of options pop up:

Electronically Interlocking Radio Buttons (*improved!*)

Electronically Interlocking Radio Buttons (*improved!*): The term "radio buttons" comes from the design of old car radios, where there would be a number of push buttons pre-tuned to different channels, and mechanically interlocked so that only one can be pushed in at a time. I wanted to find a...
www.instructables.com

It could be done with flip flops, and would have been decades ago, but in any remotely modern times a micro-controller makes far more sense.
 
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How many buttons? it would be easier with a parralel load shift register

The old radio buttons were mechanical.. Ali express even calls them Piano switches. LOL
 
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All right, fine.
Now that I've started thinking in flipflop terms, or at least discrete logic ICs, does anyone have a suggestion for that? And curiosity, and a knack for puzzles?

It seems it should be a small development, like 3 criss-crossed transistors instead of 2 (for a 3-way one), etc, but I'm still brain-wracking.
 
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You want to be talking to MM (MusicManager) He makes a lot of stuff like that.

If I did it it would use a small pic or a little GAL and I can output what I want from an input. But I like programming... I'm gong to do something with relays... I'll post when I'm done.
 
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You're still pretty vague about it's intended purpose, I posted a link to a radio switch in post #5, and googling gives loads of hits - but is that what you want?.

You mention a 'knack for puzzles', you're not wanting a 'quiz buzzer' set up are you?, that's something entirely different again.

If it's NOT that, then there is a circuit called a 'ring of three counter', bit like a bistable but with three stable states, and it's easily extended to be a 'ring of four' counter etc. I've no idea if that could be used to make a radio button circuit or not?, I last used one 50+ years ago (and we got it out of a book in the college library).
 
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Here is a single chip solution, 8 keys (I think based on resources left might be
able to do 32 or more). Each key debounced. I chose ISR to handle each key.
You could use onchip reg to read the key vs the ISR approach. Or a scanned mux,
many possibilities, again all onchip. The result of the key controls the DDS in turn
feeds the Wavedac to produce sine/tri/ramp/square/arbitrary to gen sound if so
desired.

 
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Sigh! "knack for puzzles" referred to the enjoyment of puzzling out the circuit!

There's no vagueness in its purpose - it's just something I've occasionally puzzled over, and finally ended up here. I don't remember why I wanted it originally.

Could you have posted just the schematic from the .circ in post #5?
Yes, I could look at a ring of 3 (etc) counter, thanks.
 
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Yes I could, but if you click on the link you get the full information and explanation.
 
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For your amusement to puzzle out how it works, below is the LTspice sim of a NAND-latch based Radio PB circuit (hint -- the 1MΩ resistor is necessary):
The SWs are NO PB switches.
The circuit is immune to switch-bounce.
Note that the output latches to its respective input, no matter the input sequence.

 
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What Nigel is referring to is called a game show circuit. You are after a variation of that, called, yes, a radio button circuit. There are many schematics for these on the innergoogle, and threads for both on other forums.

Here is one I posted on another forum. It uses a different approach that Carl's. Connecting C3 to any of the switch inputs makes that input default ON at power-on.

ak

 
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AnalogKid said:
Here is one I posted on another forum.
Click to expand...
I assume the purpose of C1 is to delay the clock until the D input has settled, but that seriously violates the MAX transition time for the clock (below), and could result in spurious operation of the FF.

The normal BJT turn-on delay should be all you need.
Also the slower 74HC374 / 74HC574 (differ only in pinout) has a more relaxed requirement for the clock transition time (≈100ns/V @5V), so might be a preferred device to use here, since operating speed certainly isn't a consideration.

Cheers

 
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Connecting large C's to CMOS pins not a good idea -

Connecting a Load Capacitance to a CMOS Output Pin | Toshiba Electronic Devices & Storage Corporation | Americas – United States

When an output pin of a CMOS IC is connected directly to a large load capacitance, its propagation delay increases. In addition, the increased charge/discharge current into or out of the capacitor might cause noise or a bonding wire burnout. Since current flows to the output parasitic diode at...
toshiba.semicon-storage.com


CMOS Logic input capacitor maximum value - Logic forum - Logic - TI E2E support forums

Hello experts, I got general question of maximum input capacitor value for CMOS logic (e.g. HC, AHC, HCT family) input pin. Sometimes, we add capacitor at
e2e.ti.com

Not sure if switch debounce needed, post #14, at minimum visual artifacts created by bounce ?

Classic Metastable state issues - https://www.ti.com/lit/pdf/sdya006

Trise Tfall issues in CMOS - https://www.ti.com/lit/scba004
 
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Well, you threw a much of spaghetti on the wall but none of it really sticks:
danadak said:
danadak said:
Connecting large C's to CMOS pins not a good idea -
Click to expand...
Click to expand...
There is no capacitor on the output.
The input capacitor is only charged during the PB on time, and discharges through R1, not the substrate diode.
danadak said:
Not sure if switch debounce needed, post #14, at minimum visual artifacts created by bounce ?
Click to expand...
No.
Once the FF is latched it stays latched, so further contact bounces have no effect on the output.
danadak said:
Classic Metastable state issues
Click to expand...
Any metastable states are too short in duration to have a noticeable effect on this circuit.
 
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More pasta for you :

The input capacitor is only charged during the PB on time, and discharges through R1, not the substrate diode.
Click to expand...

That depends on how Vcc is removed by user power supply. Eg. whether parasitic diode involved
(discharge thru substrate path) or your R1 dominates the discharge behavior. Does Vcc go open circuit or is it experience a switch to ground DC path that winds up discharging cap thru internal
parasitic diodes.



Its great the logic you use has none of these issues when setup and hold times not met.
But the manufacturers published guidance not in agreement.



Really ? Odd that manufacturers application notes dont call this out. But I stand corrected with
measured and characterized results you have established thru investigation.....oh wait.....

Regards, Dana.
 
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danadak said:
Really ? Odd that manufacturers application notes dont call this out. But I stand corrected with
measured and characterized results you have established thru investigation.....oh wait.....
Click to expand...
If clock input oscillates with this particular circuit - what effect can there be other than re-latching the same pressed button, which has zero effect on the wanted function?

I agree the proper clock signals are important when processing fast changing signals - but not in something like this, with a manual button providing the input?

KISS principle; if any hypothetical malfunction has no detrimental effect at all, it's not a real world malfunction.
It could have a schmitt trigger RC delay instead, but that's just over-complicating it.
 
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danadak said:
That depends on how Vcc is removed by user power supply.
Click to expand...
It would have to be removed during the time the PB is pressed since that's the only time the capacitor is charged.
danadak said:
Its great the logic you use has none of these issues when setup and hold times not met.
But the manufacturers published guidance not in agreement.
Click to expand...
Sorry, but that what does that mean?
Setup and hold are not an issue here, even if the switch bounces.
danadak said:
Odd that manufacturers application notes dont call this out. But I stand corrected with measured and characterized results you have established thru investigation.....oh wait.
Click to expand...
Page page 4, 6, and 7 of your referenced Metastable document show the time-frame for the metastable occurrences.
Oh wait, do you think that short time would be a problem here?
 
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