Steve Miller
New Member
I am using a quadrature decoder to drive an up/down counter that has dual clock inputs. There are two of these and the outputs from the 2 counters are added together. The decoder outputs are High until it pulses Low and then returns High, this is the rising edge that clocks the counter.
Everything works just fine, but, in an attempt to simplify the circuit, I came up with a different circuit that has both of the decoders driving just one counter, instead of each decoder driving it's own counter and then adding the 2 together.
It was set up so if it sees 2 "up" counts at the same time, it would allow the decoder output pulse to increment the counter, then fire a one shot to pulse it a second time. The same applies if it sees 2 "down" counts at the same time. It just fires an extra clock pulse to either the counter's UP or DOWN input, but, if it sees 1 decoder trying to count up while at the same time the other is trying to count down (or vice-versa), then it ignores both.
The added logic IC chips didn't really simplify it very much, but I wonder if it could be better simplified using a CPLD.......which is a whole new problem of it's own because I know little about them.
During testing of the up/down counter being driven by 2 different quadrature decoders, everything was working fine......until it failed.......missed/added counts, etc.
The only thing I can think of is that it failed because a decoder's rising edge happened at the same time the other decoder's edge was falling. I also wonder if the rising edge wasn't held High long enough to be valid.
Your thoughts?
Everything works just fine, but, in an attempt to simplify the circuit, I came up with a different circuit that has both of the decoders driving just one counter, instead of each decoder driving it's own counter and then adding the 2 together.
It was set up so if it sees 2 "up" counts at the same time, it would allow the decoder output pulse to increment the counter, then fire a one shot to pulse it a second time. The same applies if it sees 2 "down" counts at the same time. It just fires an extra clock pulse to either the counter's UP or DOWN input, but, if it sees 1 decoder trying to count up while at the same time the other is trying to count down (or vice-versa), then it ignores both.
The added logic IC chips didn't really simplify it very much, but I wonder if it could be better simplified using a CPLD.......which is a whole new problem of it's own because I know little about them.
During testing of the up/down counter being driven by 2 different quadrature decoders, everything was working fine......until it failed.......missed/added counts, etc.
The only thing I can think of is that it failed because a decoder's rising edge happened at the same time the other decoder's edge was falling. I also wonder if the rising edge wasn't held High long enough to be valid.
Your thoughts?
