Here is one approach. To count down a normal crystal frequency to a 3.7 day period takes 34 stages of binary counters. That's two chips, plus some decode logic.
1 CD4521 - this is a 24 bit counter that can work with a 32.768 kHz "watch" crystal. Only the last 7 bits are available, but that's enough for reasonable precision.
1 CD4040 - this is a 12 bit counter with all bits available.
19 small signal diodes like 1N914 - these are used to decode the counter state that is closest to the correct period for one phase.
1 CD4017, drivers, and LEDs to make the phase display.
One moon phase lasts 319,032 seconds, and one second is 32,768 counts of the crystal oscillator stage. So when the counter reaches 10,454,040,xxx (decimal), that number is decoded and used to reset the big counter and increment the 4017. This is about 80% of the overall counter's full range. It's not as scarey as it might sound, and it is more stable than either phase locked loop (PLL) or direct digital synthesis (DDS) techniques. Decoding only the top 19 bits of the 34 bit counter adds 4 seconds per month to the system error budget.
EDIT: Here is an updated schematic with full decoding and decoupling, missing the displays. For the decoded binary value that equals the transition of phases, the upper group of diodes connects to the ones and the lower group connects to the zeros. The decoded output of large ripple counters usually has some small glitches caused by timing skew in the bit transitions, so this circuit has an RC filter that also acts as a pulse stretcher for the advance/reset signal.
ak