Modeling Microcontroller Load

[Suudy]

So I'm trying to learn power supply design. I'm playing with some SMPS examples and tutorials. The examples I have found just show a generic load, capacitive load, or a resistive load. I've even seen resistors in parallel w/ a current source.

How does one typically model a microcontroller circuit load? I can read the datasheets and see the maximum current, but of course the load is dynamic. I presume also I can throw a large capacitor that is the sum of all the bypass caps plus the input capacitance on the source circuits. So I guess there are two questions:

1. How do I model the max load? Just the total capacitance w/ a current source in parallel, then a DC point?
2. How do I model things across time? Perhaps make the current source a PWL type and run a transient analysis?

Thanks!

 

[Papabravo]

Admittedly things were easier back in the dawn of time before CMOS processes dominated the integrated circuit landscape. Bipolar technologies were much easier to estimate and did not vary much in operation. CMOS on the other hand is sensitive to Vcc and clock speed. The dependence on Vcc is quadratic which explains why high-performance processors operate at 1.8 volts and lower. A CMOS processor can run from almost DC to the speed of blue light. Running at almost DC means the power consumption will be insignificant, while at the speed of blue light, you might need to own the power company. Testing and monitoring are about the only way to be certain.

 

[danadak]

Fast, Accurate Power Modelling - MICRO21 Best Paper

APOLLO achieves fast, yet accurate power-modelling for both design- and runtime power-introspection within the same unified framework.

community.arm.com

https://www.princeton.edu/~mrm/tutorial/hpca2001_tutorial.pdf

Wordpress | iSolutions - Service Status | University of Southampton

www.arm.ecs.soton.ac.uk

One could do a pencil and paper investigation to get at rough model, where is most and least
of the power, and eliminate the minor contributors. Obviously the cpu itself, one could from
clock rate and max Idd infer equivalent C. But that of course leaves out code, what it is doing,
does it shutdown idle hardware, what is firmware doing, ......Or delve so deep you never surface,
as ARM discusses in that paper, take the complete verilog RTL design, with actual distributed C, and
test code, what the model looks like room T. Pile onto top of that all I/O loading, phase of the
moon.....

Regards, Dana.

 

[Papabravo]

Leaves me SMH.

 

[Suudy]

In real life I'm a contractor for FPGA based designs (using Verilog), but I'm trying to expand my knowledge base. This analog stuff is a challenge.

Here's what I'm trying to understand. I don't want spend a bunch of money on a board only to have it fail. I'm trying to simulate before I build. We do this w/ digital designs all the time.

Is there no answer? "Testing and monitoring" requires me to build something. Say I pull from a datasheet, something simple like the PIC24, and it says at 3.3V @ 25C it draws 20mA max (see here, table 27-4). How do I model this?

Say even I use an LDO. If I put down an LDO with an output bulk cap, do I put the PIC24 "load" as a current source of 20mA? Seem like that doesn't work as it would be at 0V on the output. Perhaps a 100ohm load in series w/ the current source?

 

[rjenkinsgb]

Say I pull from a datasheet, something simple like the PIC24, and it says at 3.3V @ 25C it draws 20mA max (see here, table 27-4). How do I model this?

A 165 Ohm resistor?? Or 150 to give a bit of overhead allowance. KISS principle!

In reality you have to also allow for the worst-case load, adding in the current total from whatever may be connected to the MCU outputs as well.

I also always way over-rate power components & decoupling caps, "brick outhouse" grade build for everything. I don't even use single VIAs if there is room for two or three in a signal trace, or a grid of them on power traces.

That may not be good for consumer goods where cost is everything, but for industrial gear making it to last decades gets you a good reputation and loyal customers!

 

[Suudy]

A 165 Ohm resistor?? Or 150 to give a bit of overhead allowance. KISS principle!

So just take the spec'd current at the operating voltage? So in this case, you did 3.3V/20mA = 165ohms.

That's it? I understand this isn't modeling the dynamic case, but perhaps worst case? Huh. Seems too simple.

For transient simulations, this works as well, but also include the decoupling caps and input capacitance of the power rails?

Thank you!

 

[ZipZapOuch]

So just take the spec'd current at the operating voltage? So in this case, you did 3.3V/20mA = 165ohms.

That's it? I understand this isn't modeling the dynamic case, but perhaps worst case? Huh. Seems too simple.

For transient simulations, this works as well, but also include the decoupling caps and input capacitance of the power rails?

Thank you!

Use the 150 ohm resistor and add an appropriate inductor in series and a capacitor to ground. The datasheet may let you know the capacitance of the output and, if not, you should be able to estimate capacitance with the rise time and fall time of the switching (that should certainly be in the datasheet).