MAXIMUM SAMPLING FREQUENCY OF TMS320f28377S

[Shadow_warrior]

Can someone tell me the maximum sampling frequency of tms320f28377s a microcontroller from TI
Here is the link:
https://www.ti.com/product/TMS320F28377S
I am sensing a 20 KHz switching current and feed it to ADC. How many samples will I get?
Thanks in advance.

 

[dknguyen]

datasheet page 98, adc electrical characteristics. ADC conversion cycles is how many clock ticks per conversion, then the ADC has a maximum clock speed that drives it.

 

[Shadow_warrior]

datasheet page 98, adc electrical characteristics. ADC conversion cycles is how many clock ticks per conversion, then the ADC has a maximum clock speed that drives it.

tHE MAXIMUM CLOCK IS 200mhz. Does it mean it can sample at 200MHz. I am sort of a rookie in micro controllers.

 

[dknguyen]

tHE MAXIMUM CLOCK IS 200mhz. Does it mean it can sample at 200MHz. I am sort of a rookie in micro controllers.

No. 200MHz is the maximum clock speed of the CPU, not of the ADC module. The ADC module runs off a slower clock. That's why it has a different max clock speed. This is listed in the same section in the datasheet. The ADC also takes more than one ADC clock cycle to do a conversion so it can't sample at it's own clock speed either.

You have the oscillator (like a crystal) which feeds into the PLL. The PLL multiplies that clock frequency. From there the clock frequency can get routed around to different things like the CPU and ADC, but before going to certain places it is stepped down again since not everything can run as fast as the CPU.

 

[ronsimpson]

10.1.3.1 Clock Configuration
The base ADC clock is provided directly by the system clock (SYSCLK). This clock is used to generate the ADC acquisition window. The register ADCCTL2 has a PRESCALE field which determines the ADCCLK. The ADCCLK is used to clock the converter.
In 16-bit mode, the core requires approximately 29.5 ADCLCK cycles to process a voltage into a conversion result, while in 12-bit mode, this process requires approximately 10.5 ADCCLK cycles. The choice of resolution will also determine the necessary duration of the acquisition window, see Section 10.3.2.

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