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Logarithmic amplifier design for measuring the ON voltage of a GaN transistor / Schematic, Ideas and LTspice simulations available

jm_sanz

New Member
Good afternoon,

First post here and bring an exciting analog design challenge of power electronics mixed with RF :).

As you know measuring with an oscilloscope the ON-state voltage of a transistor is very challenging as the dynamic range (tens of mV to hundreds of volts) is very large and regular passive probes along with oscilloscopes don't have sufficient capabilities/bits to address this task. They cannot measure high voltages and very low voltages at the same time. People have built tons of ON-state voltage measurement circuits (OVMCs) for clipping the OFF-state voltage mainly through Schottky or Zener diodes so that a custome probe only measures the ON-state voltage. Here an example of the results of a commercial product:
1701888847517.png

However, all circuits, like this one, face the same issue... They are blind in the switching time due to their limited bandwidth. This is due to the recovery time of this clipping diode which can be large and, if an amplification circuit is needed, also the desaturation of the opamp. The bandwidth of the the OVMCs is normally aprox. 50MHz while the switching harmonics can get to 500MHz in new generation power devices (GaN and SiC).

I have been thinking on a different strategy by using a high frequency logarithmic opamp where no clipping or saturation is made at all and the entire dynamic range is measured in one custome probe. OFF-state high voltage would be highly attenuated while ON voltage would be amplified. There would be no clipping or saturation of the opamp. However I am not sure about the feasability of this design.

My target device under test (DUT), for how challenging it is, would be the EPC2088 GaN (100V@3mOhm) device going up to 80V with currents from 1A up to 20A and measuring it with the 50 Ohms input of the oscilloscope (12 bits, max 5V). This kind of transistors can have rise/fall time of 2ns. I have already built and validated a prototype of half-bridge (for measuring it in real operation) and a PCB for testing the classical methods and even a basic discrete log amp amplifier but would like to know your opinion.

I am mainly worried about the worst case of 1A for this 3mOhm device. This would equal to 3mV and our probe should measure up to 80V. I have thought of placing some large power resistor in paralel with the DUT to attenuate all voltages and face this with a regular high performance opamp but low voltage level would be very close to the noise levels.

I have also seen some information from Analog Devices of High Frequency Log Amps with integrated circuits like the AD8306S but not sure with the could stand that high rise/fall times in the inputs.

Any recommendations?
Found this task feasable?

My generic design comes with the LTC6269-10 opamp, BFP460 NPN bipolar transistors and BAT54K for the Schottkies (this circuit would be able to perform multiple OVMC, the temperature effect on the NPN is not compensated in this circuit as it is made for concept validation):

OVMC.png

I also attach one example of working LTspice simulation with the DUT and an example of clipping OVMC with a Schottky diode and a amplification circuit for the 50 Ohms oscillocope reading.

Would very great if you could provide you your insights about this challenge :).

Best regards,

José Miguel.
 

Attachments

  • OVMC LTspice Sim with Clipping.zip
    8.7 MB · Views: 65
ringing gate damping maybe? Check current spike.
 

Attachments

  • Dynamic RDSon LTC6268-10-RgD.asc
    4.6 KB · Views: 62
When I look at "on voltage" I am not looking for 500mhz bandwidth or any voltage above 10 volts. I do not understand much of why you are building this circuit. I use a 100:1 probe to look at high voltage at high bandwidth. For the on voltage, which is well under 10V, I make a circuit much like the "commercial product:" in post #1. It probably has not much more than a diode and 9V battery. I have made these for more than 40 years.

Maybe we are measuring very different things. I am looking to measure the on_resistance of the MOSFET or the saturation voltage of a transistor. Even with GaN and switching at 1mhz, I don't look at 500mhz harmonics (when the transistor is on).

Usually I have the scope picture set for -1V to 10V and maybe -1 to +1V. The high voltage is clipped off. Some MOSFETs do not turn on well for 1uS. So I have two inputs to the scope. One looks at the high voltage (100 through 2kv) and the other only looks at voltages in the -5 to +10V range. I agree that the switching edges have high bandwidth. I am looking at KV/nS. The On_Voltage has a much lower bandwidth. (I look at the RR of the internal diode and the RDS_on verses time and RDS_on verses current which happen at low voltage.)
 
When I look at "on voltage" I am not looking for 500mhz bandwidth or any voltage above 10 volts. I do not understand much of why you are building this circuit. I use a 100:1 probe to look at high voltage at high bandwidth. For the on voltage, which is well under 10V, I make a circuit much like the "commercial product:" in post #1. It probably has not much more than a diode and 9V battery. I have made these for more than 40 years.

Maybe we are measuring very different things. I am looking to measure the on_resistance of the MOSFET or the saturation voltage of a transistor. Even with GaN and switching at 1mhz, I don't look at 500mhz harmonics (when the transistor is on).

Usually I have the scope picture set for -1V to 10V and maybe -1 to +1V. The high voltage is clipped off. Some MOSFETs do not turn on well for 1uS. So I have two inputs to the scope. One looks at the high voltage (100 through 2kv) and the other only looks at voltages in the -5 to +10V range. I agree that the switching edges have high bandwidth. I am looking at KV/nS. The On_Voltage has a much lower bandwidth. (I look at the RR of the internal diode and the RDS_on verses time and RDS_on verses current which happen at low voltage.)
Yes, fully agree that for the measurement of the RDSon, clipping with a diode is the most usefull technique. However the intention of this circuit goes beyond that. I would like to have more detail on this reverse recovery process (little negative and positive ringing) as it has a really strong impact on the actual switching losses. Therefore, yes, probably measuring 80V is not needed but probably fixing it between +-5V yes. However if you want to measure it with precision, you can not use a diode as clipper as you would loose all the detail.

For this, I was thinking on a log amp or maybe using the amplification by sections like in the attached picture. Had any experience with these circuits before? Would you see it feasable?

Thanks for the help!
 

Attachments

  • Amp_Frames.png
    Amp_Frames.png
    436.9 KB · Views: 57
ringing gate damping maybe? Check current spike.
Did you try my improvement? When ringing can't be suppressed with a drain clamp due to very low RdsOn and high Q, the next best thing is to reduce risetime spectrum below resonance to reduce ringing as long as package losses are not significant. Ultrafast low pF Recovery diodes may help.
 
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Did you try my improvement? When ringing can't be suppressed with a drain clamp due to very low RdsOn and high Q, the next best thing is to reduce risetime spectrum below resonance to reduce ringing as long as package losses are not significant. Ultrafast low pF Recovery diodes may help.
Hello Tony, the thing is that my target is not to supress the ringing. The target is to see it in more detail, mostly in the turn on along with the ON voltage (for RDSon). In addition, for GaN devices, it is not recommended to use a diode on the gate, even if fast, due to their voltage drop. This is due to the low threshold voltage of this kind of devices. It is better to use a driver with two independent outputs. In my actual circuit, I am using the the LMG1205 from Texas Instruments. The one on the simulation is more for illustration purposes of the small rise time challenge.



Thank you for you comments though, I appreciate your time.
 
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Switching 30A/ns brings a lot of challenges to EMI and large signal SNR captures for OVMC for low ESL, low Coss, low Zo, low Crecovery, with Coss*ESR=Tau etc.

Given your example load of 70V/30A = 2.3 Ohms and 2 ns current rise times, lowering the ringing most certainly improves the accuracy of OVMC.

100 pH and 450 pH are certainly good numbers but what would take to reduce these numbers significantly in Cu real estate? I don't know your board geometry, but lets use ESL = 1 nH/ mm using conductor width/height ratio of h/w=30mm/2mm = 15, Zo ~ 175 ohms. The component C will be much greater than the trace C. so reducing current risetime and RdsOn are both important as well as ringing to prevent parasitic turn-on. Thus reducing ESL is just as important as reducing net load Ceff.

But to do that, you need to change trace to ground h/w ratios. This assumes Er = 4.6 and there are variables for absolute values, so is just a guide and not an absolute. Ref Saturn PCB tool.

h/w = 15, Zo ~ 175 Ohms, Lo = 1.0 nH/mm
h/w = 0.1, Zo ~ 15 Ohms, Lo = 100 pH/mm, Co = 0.5 pF/mm
h/w = 0.05, Zo ~ 8 Ohms, Lo = 54 pH/mm, Co = 0.86 pF/mm

Thus fatter traces and thinner dielectric is better for switching low impedances to reduce Zo or more importantly, reduce parasitic ESL (Lo).

Also Super fast recovery diodes. https://www.mouser.com/datasheet/2/849/bav100-2577308.pdf

If you want to measure device temperature, you can also sense peak gate current with a sense resistor to improve monitoring circuit performance.

For the OVMC board it is high impedance inputs with control impedance signals and cable lengths perhaps > 1/4wave, so impedance matching with TDR electrical testing is most important perhaps using semi-rigid coax for permanent fixtures like any any good SA, NA.
 
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If the whole purpose of the OVMC is to measure power dissipation and Rdson characteristics limited by the dynamic range of Vds which is then multiplied by Is.

Why not lower the clipper voltage threshold with a cascaded RD divider ?
If not what are realistic specifications for a better OVMC for BW, dynamic range, gain. with CMLdiff or CMOS OA linear amplifers, then you avoid the calibration errors of log power and diode Q.
 
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