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latch and flipflop

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vencatesh said:
i need to know what is difference between a latch and a flip flop.

The 74LS74 is a Flip-Flop. Here is a data sheet online:
https://www.electro-tech-online.com/custompdfs/2007/05/74LS74.pdf

The Flip-Flop (AKA F/F) has a clock pin, data pin (input, called 'D') and an output pin (called 'Q'). This particular IC waits for a positive (rising) edge clock signal to latch the logic level at the data pin to the output pin. The clock pin is ignored after that until it goes low then rises again. Some F/Fs use a negative-going (falling) clock edge.
Each data pin on the '74 actually gets stored to two output pins, in a situation called "complementary outputs". One output is the original latched level; the other is the opposite, or inverted, level.

The 74LS75 is a latch. Here is a data sheet online for it:
https://www.electro-tech-online.com/custompdfs/2007/05/74LS75.pdf

The latch's operation is based on the logic level of its ENABLE pin (called 1C, 2C, 3C and 4C in the data sheet pin out). When the #C pin is high, any logic level at the input (pin #D) is passed to the output (#Q). As soon as #C goes low, the #D input "latches" to the #Q output. This continues until the ENABLE pin (#C) goes high again, thus letting any signal pass on immediately.
You will note that the 74LS75 also has complementary outputs.

Note that, like most flip-flops, the '74 has extra inputs (CLR#, called CLEAR, and PR#, called PRESET) that are used to force all outputs to the same level. CLR and RST (for Reset) force normal outputs low; PR forces the outputs high. These pins on the '74 work on a simple low logic level.
As far as other F/Fs in general, these inputs can be low or high true, and may work immediately with a simple level or work only as the clock fires ("synchronous" operation). These are used when the operator wants to force the outputs to a known level, usually at power up.
If you don't need to use these in your design it is a good idea to connect them to the non-enabling levels. So, in the case of the '74, the CLR and PR pins would be pulled high, preferably with a pullup resistor in the range of 10k to 47k Ohms (for TTL).

Hope that helped.
kenjj
 
thanks for replying..
what i understood from ur explanation is flipflop is edge triggered whereas latch is edge triggered.

is there any other difference.
 
one more question

i read a latch consists many flip flops
and in another article that a flip flop is made of many latches .
Which is correct of the two statements and why.
 
vencatesh said:
one more question

i read a latch consists many flip flops
and in another article that a flip flop is made of many latches .
Which is correct of the two statements and why.

hi,
The term flip-flop F/F is used to describe a Bi-stable device.

A single Bi-stable can have an high output state or low output state. ie: '0' or '1'.
The output state is switched over for each clock input.

So it could be considered as a one bit latch, that is, its output state holds [latches] the current output state. [until powered off]
If you had say 8 bi-stables, they could be wired as an 8 bit latch, their output states representing an 8 bit byte.

A Bi-stable, can also be configured as a divide by 2, each clock input pulse changes the state of the output, '0' or '1'.
If this output is connected to the input of a second bi-stable, the output of this second bi-stable is the clock input to
the first bi-stable divided by 2 * 2 =4. and so on.....

There are many different configurations of Bi-stables, they can be wired as latches, dividers.

There are also 'transparent' latches, when the ic's Enable/Strobe line is say a low state, the latch outputs follow their respective
inputs, when the Enable/Strobe line changes state the outputs are latched and the inputs are ignored.

They come in many different ic packages or thay can be configured using individual logic gates or transistors.

Does this help?
**broken link removed**
 
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