Latch LS374 works for sometimes and doesn't work at all next clocks

[ahmedragia21]

I'm trying to interaface with an 8080bus, that's the schematic of the socket of it:
I'm latching all of the signals, A1,CS1,CS2, IOWR as clock to LS374, and the databus.
Here is the schematic of the board that has the two latches connected

I'm powering the latches from STM32F429I Discovery board, 5V, GND. The ground of the Device 8080 is connected to STM32Board and to the PCB of the two latches.
I captured the data using logic analyzer, here is the data:
MPC LATCH IOWR
6E 30 1
7E 30 1
7A 30 1
21 30 0
21 30 1
21 21 1 <--- latch is valid here
7F 21 1
7E 21 1
7F 21 1
7A 21 1
6A 21 1
7A 21 1
71 21 1
61 21 1
66 21 1
76 21 1
7A 21 1
6A 21 1
7A 21 1
78 21 1
68 21 1
60 21 1
70 21 1
76 21 1
7F 21 1
6F 21 1
60 21 1
7F 21 1
6F 21 1
61 21 1
7D 21 1
6E 21 1
78 21 1
7F 21 1
6F 21 1
6A 21 1
7A 21 1
71 21 1
61 21 1
68 21 1
78 21 1
74 21 1
24 21 1
21 21 1
6F 21 1
62 21 1
72 21 1
7A 21 1
79 21 1
69 21 1
63 21 1
7F 21 1
78 21 1
79 21 1
69 21 1
6E 21 1
67 21 1
77 21 1
7D 21 1
6D 21 1
6F 21 1
7F 21 1
76 21 1
66 21 1
60 21 1
70 21 1
78 21 1
7A 21 1
6A 21 1
61 21 1
70 21 1
73 21 1
3E 21 0
3E 3E 1 <--- latch is valid here
7F 3E 1
70 3E 1
7E 3E 1
6F 3E 1
60 3E 1
70 3E 1
78 3E 1
68 3E 1
60 3E 1
70 3E 1
77 3E 1
67 3E 1
6F 3E 1
7F 3E 1
70 3E 1
75 3E 1
65 3E 1
6E 3E 1
7E 3E 1
7A 3A 1 <--- latch is corrupted here
20 12 1 <--- latch is corrupted here
20 3A 0 <--- latch is corrupted here
20 20 1
7F 20 1
75 20 1
65 20 1
6F 20 1
7F 20 1
77 20 1
67 20 1
69 20 1
79 20 1
7F 20 1
6F 20 1
7F 20 1
70 20 1
68 20 1
78 20 1

I have no idea what's going wrong, and why the latch works for few moments and then is corrupted.

 

[aliarifat794]

From the provided logic level analyzer data, the latch appears to work initially but then becomes corrupted. If possible, use an oscilloscope to check the timing of the control signals and the data bus relative to the latch enable signal (IOWR).

 

[danadak]

What power rail bypassing are you using for each logic part and type
of capacitor ?

If you have a DSO place it on infinite persistence, and monitor a power rail
to see what pk-pk noise looks like.

Regards, Dana.

 

[ahmedragia21]

danadak
I'm not using nay bypassing. I don't have DSO

 

[danadak]

No bypassing fast logic = disaster.

 

[ahmedragia21]

danadak
Which cap should I put and how much ?

 

[danadak]

As close as possible to power pins of LS374, a .01 and .1 uF ceramic disk.

Show a picture of your prototype boards/layout. Well focused and post it.


Regards, Dana.

 

[ahmedragia21]

danadak

 

[danadak]

Is there a ground plane in that layout ? Where one leg of caps tied close to power
pins of logic, the other into the ground plane ?

See attached doc on layout.

 

[rjenkinsgb]

This has already been asked and answered, here:

Using latches to capture 8086 bus

I'm trying to capture the data using stm32, I have used two latches as the following diagram and this is the schematic of the bus for your reference I'm not getting any LCD commands that was referenced in the answer, I only get two LCD Commands 0x60, and CS1,CS2 = 1, A1 = 0 or 1, and they are...

www.electro-tech-online.com

As shown you are trying to capture every I/O write cycle from the MCU, rather than only ones relating to the LCD data bus.

 

[ahmedragia21]

rjenkinsgb
I'm filtering that in software, why do I need logic gates ?

 

[rjenkinsgb]

I'm filtering that in software, why do I need logic gates ?

Speed!

There could be consecutive write cycles to the LCD and other peripherals within microseconds, so the latched data may change again before it is read.

The /IORD and /IOWR signals are used for any and every peripheral device in an 8080 system.

If you are trying to capture the LCD data, you need to replicate the gating created by the other signals used for that.

 

[ahmedragia21]

rjenkinsgb
The LCD is only written to when /CS1, /CS2 and /IOWR are ALL low. Looking at the signals separately is meaningless.

This is from your original post. This assumption is incorrect. LCD data is only written when IOWR or CS1,CS2 is active.

 

[rjenkinsgb]

Remember I've not seen the device you are monitoring, only the circuit fragment! It's not at all unusual for ICs to have more than one CS input, with internal gating.


If the LCD is a dual controller type, with two separate ICs rather than a single IC that has two /CS lines, then the gating logic for the /CS lines would be different, but gating logic is still required.


You would need an active low OR gate (= AND gate) to produce a common /CS signal, then an active low AND (= OR) gate to combine that with the /IORW and take that to the latch enable.

Also take one of the incoming /CS lines to a latch data input; that can be considered an extra address line, as it will be high or low depending on which driver IC is being accessed.


Practical logic could be a NAND gate to combine the two /CS inputs (giving high on access), another NAND as an inverter from the /IORW (so giving high on write) then both those to a third NAND, giving a low for the latch clock.

 

[Papabravo]

An LS374 is NOT a latch it is an octal Flip-flop which clocks data on the rising edge of the clock. The LS373 is an octal latch which is transparent when the latch enable is high and latches on the trailing edge. Which of those two possibilities did you actually intend?

ETA: In order for a clocked flip-flop to work you need to verify that bot setup and hold time restrictions are met. It is likely the setup time requirement is easily met, but the hold time restriction could be a problem. If you were actually using 74LS373 LATCHES with an inverted IOWR* as the latch enable signal I think you might have a better chance of getting the results you expect.

Just to be clear was this an 8080 bus or an 8086 bus?

 

[ahmedragia21]

Papabravo
Thanks so much!, it's a 8086 CPU, old architecture.
What If I don't have an inverter with my hands now ? How can I overcome that ? I have also LS373 right now with me now, in addition LS374.

 

[ahmedragia21]

Papabravo
rjenkinsgb
here is the datasheet of the CPU

UPD70236 PDF

Part #: UPD70236. Description: 16-Bit Microprocessor, High-Speed, High-Intergration, CMOS. File Size: 7317.32 Kbytes. Manufacturer: NEC.

pdf1.alldatasheet.com

 

[danadak]

An LS374 is NOT a latch it is an octal Flip-flop which clocks data on the rising edge of the clock. The LS373 is an octal latch which is transparent when the latch enable is high and latches on the trailing edge. Which of those two possibilities did you actually intend?

ETA: In order for a clocked flip-flop to work you need to verify that bot setup and hold time restrictions are met. It is likely the setup time requirement is easily met, but the hold time restriction could be a problem. If you were actually using 74LS373 LATCHES with an inverted IOWR* as the latch enable signal I think you might have a better chance of getting the results you expect.

Just to be clear was this an 8080 bus or an 8086 bus?

Actually the industry seems to indicate D F-Fs can function as a latch, eg. the definition
of what it means to store data. TI datasheet distinguishes 373 as latch, 374 as D F-Fs.
But googling generally speaking D F-Fs can be used as "latches". Looks like we need
"latch" def police to get busy .

digital logic latch at DuckDuckGo

DuckDuckGo. Privacy, Simplified.

duckduckgo.com

 

[ahmedragia21]

Would connecting a CPU IO to invert signal and feed it back to LS373 work ?
I don't have an inverter now

 

[ahmedragia21]

would that inverter work ?

https://www.ti.com/lit/ds/symlink/cd4010b.pdf?ts=1722598160395&ref_url=https%253A%252F%252Fwww.google.com%252F

How do I connect it please ?