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Influence of the clock's quality on setup's times

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Hi,

I'm searching for some material (papers, slides, books' chapters, etc.) that talks about the influence that the clock's quality has on setup's times and other timing charateristics.
I've tried to search online, but I've not found much.

I'd be very grateful if you could give me some direction :)

Thanks in advance,
Pierpaolo
 
As you can see in this figure:
clock.jpg

this signal clock has indeed a clock shape, but has some imperfections too (on the rising and falling edges, plus some additional noise). I've heard that these imperfections could lead to different output's timings for some logic (flip-flop, shift-register, etc.). I'm looking for confirmation by reading some papers, books, or anything.
 
First some of you clock shape might be you scope probe and grounding.
There is a voltage range hat equals a 1, a range that equals a 0 and a range that is uncertain. Each family of logic has its own range. TTL, CMOS, LVTTL, ECL,

You need to stay out of the uncertain area or pass through it as fast as possible.
When you are with in a good area it really does not matter what happens. Example: if anything above 2 volts =1 then noise at 4.8 volts =1. If below 0.8V=0 then noise at 0.2 has no effect.

You should never ring back into the uncertain area!

I think your picture look good.
 
Datasheets for logic ICs etc should inform you as to clock requirements, e.g. leading edge rise rate.
 
There are two major areas of concern dealing with rising and falling edge quality. Google "clock jitter" if you want to investigate a third clock quality problem. Depending on your clock driver and the signal trace layout, reflections can cause changes in the rising and falling edges. These changes are normally changes in slope of the clock edge. Simple cases just slow down the rise time, in high speed designs, this unexpected delay can cause you to miss your set up times (or hold times if it is a falling edge clock problem).

In severe cases, the rising edge can actually change to a downward slope and then back up again (and the inverse of this on falling edges). This could result in double clocking (a single rising edge is detected as two rising edges). This condition is pretty hard to create: poor driver current sourcing, no clock termination, and bad clock routing. But I've seen it occur (always on someone elses design, just to keep the record straight).

But you should be looking in the nanosecong or 10's on nanosecond range. And your scope should have at least a gigahertz of bandwidth in order to get a realistic view of what your rising and falling edges actually look like. Good scope probes with low capacitance are a must if you are actually trying to debug a problem like this.

One final area that might actually affect you at lower clock rates is the falling edge ringing bad enough to be seen as a string of pulses. Again, pretty tough to create this. Put a series termination resistor at the clock driver and you will be able to prevent this in most situations.

looking at your image, you may just be seeing a digital scope display problem. Speed up the scope and look very closely at each edge for any slope anomalies.
Is this what you were looking for?

JimW
 
As you can see in this figure:
clock.jpg

this signal clock has indeed a clock shape, but has some imperfections too (on the rising and falling edges, plus some additional noise). I've heard that these imperfections could lead to different output's timings for some logic (flip-flop, shift-register, etc.). I'm looking for confirmation by reading some papers, books, or anything.

High Frequency Accentuation (Over Compensation)
Over Comp.png



High Frequency Attenuation (Under Compensation)
Under Comp.png


Correct Compensation
Normal Comp.png


All 3 are the same waveform with only the probe compensation being adjusted.

Ron
 
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