Home made high speed JTAG

[rmileca]

Home made JTAG

Hi All

I found this site: Welcome to Open JTAG Project

It may be of interest to someone.

 

[BrownOut]

Thanks For Sharing

Yes, I'm very interested. JTAG is my main gig.

Wish they provided more details, and why is it not possible to get a USB device that operates at full speed?

 

[rmileca]

They are using the FTDI245BM, and this chip is full speed (12 Mbps). should be high speed

 

[rmileca]

Sorry... full speed

 

[BrownOut]

Then why does the DATASHEET say 1 MBps?

I guess 8mbps isn't too bad.

 

[rmileca]

Realy is not bad. The CPLD accept bytes from the FT245 and serialize inside, reach TCK at 24 MHz, and it is NOT BAD!!

Weeks ago I emulate the Open JTAG board using my Altera MaxII development board and the project work fine.
But is better wait for OpenOCD support. Seems that the openjtag team is working on

 

[BrownOut]

Realy is not bad. The CPLD accept bytes from the FT245 and serialize inside, reach TCK at 24 MHz, and it is NOT BAD!!

TCK @ 24MHZ for bursts, since the FT245 can't keep up at only 8mbs. Are you using a FT245 dev board like this with your Altera dev board, or is the chip resident on the Altera board?

 

[rmileca]

You are right, must serialize in burst mode. The ideal case is use a FT2232 at full speed, but I think is too expensive. They claims that the half CPLD capacity is free, ideal to find to implementate the SWD mode. Finally, the high TCK speed supported by the major devices is 4/6 MHz.

The MaxII dev board have a FT245 wired to the CPLD. I think that the entire project could be emulated using this board.

The main tip in this project is the move TAP state capability using 1 byte command. In the past, I've been working heavy using the Wiggler JTAG, and for move the TAP state I need 1 byte to high TCK, and another byte to down TCK. The Altera USB Blaster use the Wiggler method yet!!

 

[BrownOut]

Yeah, I have the same problem. I wrote my own custom software in MSVC++, and have to use two bytes just to toggle the clock. If I used a CPLD instead of the parallel-2-JTAG cable, I could get away from that, but I couldn't get away from the ultra slow parallel port. I put my system together to be very, very simple, and now I'm interested in reving it up. Since I'm using the Xilinx Spartan 3-E board, which does not have the FT chip, I'd have to use the kit and cable it to my board. I'm considering that, or else using ethernet. But since there is VHDL already written for this project, it might tip the scales towards USB